SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)

Circuit Design

• Own the design of one or more custom analog blocks from specification through schematic, simulation, and layout review — with clocking (PLL, DLL, CDR) as the primary focus and transmitter/receiver circuits as valued secondary experience.
• Contribute to top-level PHY analog architecture decisions — clocking topology, signal chain partitioning, power domain strategy, and performance/area/power tradeoffs.
• Develop and maintain transistor-level simulation testbenches; execute corner, Monte Carlo, and mismatch analysis to characterize design margin and yield sensitivity.
• Define clean interface specifications between custom analog blocks and the digital control wrapper — signal naming, timing contracts, and boundary constraint documentation in coordination with the Chip Lead.
• Work closely with the layout team to review and guide custom analog layout — matching, shielding, guard ring, and parasitic sensitivity for high-speed circuits.
• Support post-silicon characterization in the lab — correlating measured results to simulation, identifying root causes of performance delta, and extracting maximum learning from each hardware run.
• Author block-level specifications, simulation summary reports, and interface control documents that serve as the authoritative reference for the team and for follow-on program development.

Architecture Definition

• Contribute to top-level PHY analog architecture decisions — clocking topology, signal chain partitioning, power domain strategy, and performance/area/power tradeoffs.

Simulation & Verification

• Develop and maintain transistor-level simulation testbenches; execute corner, Monte Carlo, and mismatch analysis to characterize design margin and yield sensitivity.

Analog-Digital Interface

• Define clean interface specifications between custom analog blocks and the digital control wrapper — signal naming, timing contracts, and boundary constraint documentation in coordination with the Chip Lead.

Layout Collaboration

• Work closely with the layout team to review and guide custom analog layout — matching, shielding, guard ring, and parasitic sensitivity for high-speed circuits.

Silicon Bring-Up

• Support post-silicon characterization in the lab — correlating measured results to simulation, identifying root causes of performance delta, and extracting maximum learning from each hardware run.

Design Documentation

• Author block-level specifications, simulation summary reports, and interface control documents that serve as the authoritative reference for the team and for follow-on program development.

Basic Qualifications:

• BS, MS, or PhD in Electrical Engineering or related field (MS/PhD strongly preferred for this level)
• 10+ years of analog/mixed-signal IC design experience with at least one tape-out in a primary circuit ownership role
• Deep expertise in clocking circuit design — PLL, DLL, or CDR architecture and transistor-level implementation in advanced CMOS nodes
• Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis for yield-aware design
• Solid understanding of jitter analysis — phase noise, period jitter, cycle-to-cycle jitter, and their impact on high-speed link timing margins
• Experience defining analog-digital interfaces in a mixed-signal environment — including timing contracts, reset/initialization sequencing, and digital control of analog parameters
• Able to work effectively as a peer technical contributor on a small team — comfortable with broad ownership, cross-discipline collaboration, and making design decisions with real consequences
• Strong written communication skills — this role produces specifications and simulation reports, not just schematics

Preferred Qualifications:

• Experience with high-speed transmitter design — output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces
• Experience with high-speed receiver design — sense amplifiers, CTLE/DFE equalization, sampler design, and threshold calibration
• Familiarity with die-to-die or chip-to-chip PHY architectures — UCIe, AIB, BoW, or proprietary short-reach interconnect standards
• Familiarity with OTP/fuse-based calibration architectures and analog trim loop implementation
• Familiarity with real-number modeling (RNM) or Verilog-AMS behavioral modeling for use in mixed-signal simulation environments
• Post-silicon characterization experience — correlating simulation results to measured eye diagrams, BER curves, phase noise plots, and jitter histograms on real hardware
• Prior experience in a small team or pathfinding environment where the analog architecture is not handed down but actively developed

Pay Range: $159,000.00 - $347,000.00 a year