Silicon Validation Engineer 5

About the role

Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists developing programmable logic solutions that are changing the industry. This position offers an opportunity to learn and participate in cutting-edge FPGA validation projects within the Silicon Engineering team.

As a Silicon Design Validation Engineer, you will validate building blocks in FPGA at the board level to ensure functionality and performance. FPGA components include SERDES (PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5), DPHY, PLL, DSP, Fabric, I/O, and more. You will gain exposure to advanced equipment, boards, and software/tools/scripts while developing validation and characterization plans for various IPs.

Responsibilities

• Validate and characterize various IPs from silicon arrival to release to production.
• Develop validation and characterization plans for specific IPs, including bench hardware and software.
• Create test logic RTL to achieve intended validation and characterization goals.
• Drive new silicon product bring-up, validation, and debug to assess IP functionality and performance.
• Characterize data sheet parameters and analyze measured data with a statistical view.
• Prepare data sheets and documentation.
• Serve as the central resource for design, verification, manufacturing, test, quality, and marketing/apps teams as products move from silicon arrival to release.
• Support customer issues post-product release to resolve any identified problems.

Requirements

• 8+ years of experience in Silicon Design Validation or a related field.
• Electrical Engineering degree with a strong desire to pursue a career in Silicon Design Validation.
• Capability to lead small teams as a technical lead.
• Expertise in high-speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB, DisplayPort, HDMI).
• Expertise in high-speed board design and signal integrity evaluation/debug.
• Proficiency in Verilog/VHDL and FPGA development tools.
• Experience in test automation development using Python, Perl, or similar languages.
• Knowledge of statistical analysis concepts and tools (e.g., JMP, R).
• Proficiency with bench equipment for device characterization (e.g., BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers).
• Exposure to FPGA emulation/prototyping.
• Strong written and verbal communication skills for cross-functional collaboration.
• Self-motivated with proactive critical thinking and problem-solving skills.

Pay

Lattice offers a market-based pay structure that varies by location. The base pay range for this role in the U.S. is $220,800. Starting salary will depend on job-related knowledge, skills, experience, and work location.

Benefits

• Comprehensive, competitive benefits package including healthcare and retirement plans.
• Paid time off.
• Eligibility for variable/incentive compensation and/or equity.