Silicon Validation Engineer 3

Our client is seeking a Validation Engineer to join their team in the Silicon Valley, CA area. This role is local to Mountain View and requires daily onsite presence.

About the Role

The purpose of this team is to develop and validate the silicon chips that power Azure cloud services and AI workloads. This role will contribute to hands-on silicon validation activities for chip development efforts, supporting the testing and validation of silicon hardware used in Microsoft's Azure and AI infrastructure. The contractor will work onsite in the lab performing highly technical, hands-on work.

Responsibilities

• Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors.
• Extend the compile and build flow to support custom firmware-style tests.
• Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files.
• Design additional custom FPGA RTL for protocol interfaces and feature enablement.
• Release stable platforms to the firmware team and keep them working as the design evolves.
• Develop and extend custom Python tooling to interface with the FPGA platform.
• Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
• Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware, and security teams.
• Root-cause failing post-silicon tests to closure, collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs, coordinating cross-team debug, and delivering fixes such as handling fatal errors, correcting driver access violations, and reconciling registers modified by boot firmware.

Requirements

• Strong hands-on experience in SoC verification, FPGA/emulation platform bring-up, post-silicon validation, embedded software development, and hardware debug.
• Demonstrated expertise in C/C++, Python scripting, SystemVerilog-based verification environments, and industry-standard protocols such as AMBA, JTAG, SPI, I2C/I3C, and USB.
• Experience collaborating across architecture, design, firmware, and validation teams.
• Deep understanding of silicon and computer architecture.
• Must be local to the Silicon Valley, CA area and able to work onsite daily at the Mountain View campus.
• Candidates with a history of multiple short-term contracts without sufficient explanation may not be a fit for this role.

Preferred Qualifications

• Experience developing C and C++ test content for subsystem and SoC verification, including bare-metal and firmware-style tests, with working knowledge of SystemVerilog testbenches.
• Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx), including board images, platform tooling, and testbench changes that enable firmware and validation teams.
• Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
• Experience with post-silicon bring-up and validation, including running test suites on silicon and debugging boot, platform, and connectivity issues in a lab environment.
• Proficiency in Python, or a similar scripting language such as Perl or Ruby, for test automation, build flows, and log or data parsing.
• In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
• Experience with low-level and embedded software, including assembly, startup code, linker scripts, and Makefile-based build flows.
• Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB.
• Strong communication skills and experience collaborating across cross-functional teams.

Hard Skills Assessment

The assessment process will include two panel-style rounds with the sponsor and full-time employees. Candidates should be prepared to demonstrate their technical knowledge and hands-on experience relevant to silicon validation. Assessments will be scheduled as soon as possible.

Pay

$59–$63 per hour.