Serdes Characterization & Post-Silicon Validation Engineer

We need to output HTML fragment with sections: About the role, Responsibilities, Qualifications, Compensation And Benefits (maybe "Compensation and Benefits" as heading). Also maybe "Preferred Qualifications"? The instructions: Use

for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). Include a section ONLY when posting has real, specific content. So we need sections: About The Role (they have "About The Role" heading). Responsibilities (they have "Responsibilities"). Qualifications (they have "Qualifications"). Preferred Qualifications (they have "Preferred Qualifications") - that is a subsection; but we could treat as part of Qualifications? The instruction says we can have sections like Skills, but we can include Preferred Qualifications as a separate section if content present. It says "Prefer a few substantive sections over many thin ones." Might combine Qualifications and Preferred Qualifications into one Qualifications section? But they are distinct. However we could include both as separate headings if they have content. The instruction: "include a section ONLY when the posting has real, specific content for it — never emit a heading followed by filler/placeholder text". Both have content. So we can have Qualifications and Preferred Qualifications sections. Compensation And Benefits: they have "Compensation And Benefits" heading with content. So include that. Pay: they have base salary range; that's part of Compensation And Benefits. So we don't need separate Pay. Schedule: not present. Benefits: included in Compensation And Benefits. Thus sections: About The Role, Responsibilities, Qualifications, Preferred Qualifications, Compensation And Benefits. We need to use

for each heading. Use

• for any list of duties/requirements/benefits. Use

  for prose. We must preserve all substantive information, not invent or summarize away detail. Remove boilerplate: cookie/navigation/legal/EEO/equal-opportunity/scam-warning, duplicated lines, application instructions. Also remove Export Compliance, Equal Opportunity sections (they are EEO). Also remove "If you don’t meet 100%..." maybe that's encouragement but not boilerplate? It's part of posting but not a list; could keep as prose? It's not a list; it's a motivational statement. Might keep as part of About The Role? Actually it's after Qualifications? In original: after Qualifications and Preferred Qualifications they have "Compensation And Benefits" then "If you don’t meet 100%..." then "Building a spacecraft..." then "If you need a reasonable accommodation..." then Export Compliance, Equal Opportunity. We should remove the accommodation line? It's not boilerplate but maybe considered application instruction? It's about reasonable accommodation; could be considered EEO? Might be safe to remove as it's not substantive to role? The instruction: remove cookie/navigation/legal/EEO/equal-opportunity/scam-warning boilerplate, duplicated lines, and application instructions. The accommodation request is more like application instruction; we can remove. Also remove "If you don’t meet 100%..." maybe not boilerplate but it's encouragement; could keep as prose? It's not a list; but it's not essential detail? Might be considered filler? I'd keep it as part of About The Role? Actually it's after Compensation And Benefits; could be its own section like "Encouragement"? Not in allowed headings. Safer to remove it as it's not a required heading and could be considered filler. The instruction: "Prefer a few substantive sections over many thin ones." So we can drop that paragraph. Thus we need to extract content for each section. About The Role: The paragraph after "About The Role": "We are looking for a hands-on SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs. You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up." That's prose; we put in

  . Responsibilities: list of bullet points after "Responsibilities". Need to convert each line to

• . Ensure we keep all details. Let's extract responsibilities lines: - Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces. - Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions. - Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin. - Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior. - Perform BER and stress testing across representative and worst-case channels. - Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic. - Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis. - Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up. - Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting. - Support the transition from chip-level SerDes characterization to product integration and system-level validation. - Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up. We'll put each as
• . Qualifications: list after "Qualifications". Lines: - BS/MS in Electrical Engineering, Computer Engineering, or related field. - 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience. - Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets. - Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment. - Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization. - Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding. - Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces. - Strong debugging skills across silicon, package, PCB, firmware, and system boundaries. - Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams. We'll put each as
• . Preferred Qualifications: list after "Preferred Qualifications". Lines: - Experience with 112G+ PAM4 SerDes characterization and validation. - Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces. - Experience with compliance testing and high-speed interface standards. - Familiarity with SerDes behavioral/channel models and simulation-to-measurement correlation. - Experience with SerDes IP integration and validation from third-party IP vendors. - Experience with advanced package and high-loss PCB channels. - Familiarity with high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects on SerDes performance. - Experience with automated PVT characterization and large-scale measurement data analysis. We'll put each as
• . Compensation And Benefits: content after that heading: "Base salary range for this role is $170,000 – $250,000 + equity in the company Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks" We need to preserve all info. It's a bit run-on; we can split into sentences. Use

  for prose. Could also make a

  for benefits list? The instruction: Use
  • for any list of duties/requirements/benefits. So we can make a list for benefits. But we also have salary range. Could do

    for salary and then

    for benefits. Let's parse: Base salary range for this role is $170,000 – $250,000 + equity in the company. Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks. We can make a
    for benefits items: paid time off, medical/dental/vision coverage, life insurance, paid parental leave, many other perks. But "many other perks" is vague; still okay. We'll output:

    About The Role

    We are looking for a hands-on SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs. You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.

    Responsibilities

    • Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
    • Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
    • Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
    • Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
    • Perform BER and stress testing across representative and worst-case channels.
    • Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
    • Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
    • Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.
    • Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
    • Support the transition from chip-level SerDes characterization to product integration and system-level validation.
    • Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.

    Qualifications

    • BS/MS in Electrical Engineering, Computer Engineering, or related field.
    • 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
    • Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
    • Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
    • Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
    • Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
    • Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
    • Strong debugging skills across silicon, package, PCB, firmware, and system boundaries