Senior Technical Staff Engineer - Verification

About the role

Microchip Technology Inc. is seeking a Senior Technical Staff Engineer – Verification to join the dsPIC Business Unit in Chandler, Arizona. In this role, you will lead IP-level verification for dsPIC products using formal verification and UVM testbenches. You will collaborate with cross-functional teams across the USA, India, and other global corporate teams to ensure high-quality verification results and timely project execution.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability, offering unlimited career potential and nationally-recognized Leadership Passage Programs that enroll over a thousand people annually. Our company is built on a foundation of trust, empowerment, respect, diversity, and communication, driven by our Vision, Mission, and 11 Guiding Values.

Responsibilities

• Architect, develop, and maintain UVM verification environments and Formal verification environments.
• Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
• Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
• Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
• Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
• Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
• Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in functional verification.
• Strong expertise in SystemVerilog language, assertions, and UVM methodology.
• Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
• Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
• Strong communication, teamwork, and problem-solving skills.
• Highly motivated, detail-oriented, and committed to delivering quality results on time.

Preferred Qualifications

• Demonstrated success in mentoring engineers and leading verification efforts across global teams.
• Experience driving methodology improvements and automation initiatives.

Travel

0% - 25%

Physical Requirements

• Sitting: 90%
• Hearing, seeing, talking required.
• Works alone and around others.