Senior Technical Lead

Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client locations throughout the U.S.

About the Role

Verification and Validation of FPGAs, supporting project execution by reviewing engineering artifacts and ensuring verification deliverables meet design and quality requirements through timely reviews of all artifacts generated by the team(s).

Responsibilities

• Review, verify, and validate FPGAs and related requirements.
• Collaborate with cross-functional engineering teams and provide technical guidance on verification activities.
• Perform certification documentation reviews and baseline certification plans (e.g., PHAC, HVVP, HCMP, HPAP).
• Create planning documentation including Plans, PHAC, HVVP, HCMP, and HPAP.
• Develop simulation test benches using System Verilog and UVM.
• Create simulation test cases and procedures documents.
• Generate Problem Reports/Change Requests, coordinate all problem reports/change requests created by remote team(s), and drive them to closure.
• Coordinate with the Change Control Board (CCB) and participate in CCB meetings with customer technical teams to approve change requests/problem reports.
• Document issues identified in requirements and design, communicate with customer technical teams, and drive resolution.
• Communicate DO-254 certification aspects with customers and their stakeholders.
• Participate in technical reviews, implement findings, guide teams on complex issues to ensure compliance with DO-254 DAL A objectives, and drive closure.
• Participate in certification audits and compliance reviews with customer and regulatory stakeholders, document audit actions, and drive them to closure.
• Attend daily/weekly status meetings and drive team(s) to meet customer/program expectations.

Requirements

• Bachelor’s degree (or foreign equivalent) in Electronics Engineering or a related field, plus five (5) years of experience in the job offered or a related position.
• Demonstrable knowledge of:
  • System Verilog and UVM methodologies (including UVM RAL Model).
  • ASIC/FPGA verification, RTL debugging, and waveform analysis.
  • C/C++, DPI, Python, and Perl.
  • Protocols: PCIe, SPI, I2C, Ethernet, DDR, ARINC, AMBA-AXI, AHB.
  • Verification IP (VIP), HIL test setups, JTAG, and logic analyzers.
  • Tools: Synopsys VCS, Cadence Xcelium/Incisive, Mentor QuestaSim, Git, SVN, DOORS, JIRA.
  • Standards: DO-254, PHAC, HVVP, HCMP, and CCB processes.
• Travel to unanticipated client locations throughout the U.S., approximately 30%, as required.
• May telecommute from any location within the U.S.