Senior Substrate Layout Design engineer

Responsibilities

• Lead the end-to-end physical layout of high-density, multi-die substrate design.
• Design and optimize bump maps, breakout routing, via structures, and layer stack-ups.
• Collaborate with ASIC, signal integrity, and power teams to ensure clean escape routing and breakout strategies.
• Evaluate routing feasibility in co-design environments, considering die floorplans and mechanical constraints.
• Drive DRC, DFM, and manufacturing rule checks to ensure fabrication readiness.
• Interface with substrate vendors and OSATs for tape-out and manufacturability validation.
• Conduct technical reviews and iterate on layout improvements with internal and external stakeholders.

Requirements

• 6 - 8+ years of experience in substrate layout design for high-performance IC packaging.
• Proven experience expertise in organic substrate design from silicon to BGA.
• Deep understanding of chiplet-based, multi-die, and advanced packaging (FPGA, CPU, CPU, MCM, CoWoS).
• Strong collaboration skills with ASIC, signal, and power teams.
• Proficiency in Cadence Allegro APD and AutoCAD.
• Experience working with OSATs and substrate suppliers.
• Bachelor’s degree in Electrical Engineering or equivalent experience.

Pay

Salary range: $215,000 - $270,000

Benefits

• Comprehensive benefits: Medical, Dental, Vision, 401k, PTO, holidays, and sick leave as required by law.