Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

About the role

The role involves working in the Design Automation group as the technical owner of Static Timing Analysis flows and timing modeling methodology across Altera's ASIC, Custom and Semi-Custom IP designs. You will lead a small team delivering these flows and represent the timing DA domain in cross-functional methodology forums and working groups.

Responsibilities

• Real architectural latitude: Stand up next-generation characterization flows and onboard timing sign-off into a new unified flow environment.
• Breadth: Work with block-level, full-chip, transistor-level, and FPGA timing collateral.
• Represent the timing DA domain with design team leads, physical design, technology enablement, and QRE partners.
• Drive engagements with major EDA vendors, evaluating capabilities, escalating issues, and shaping roadmaps.
• Hands-on CAD role: Develop and release production-grade flows, regressions, and automation, support design teams, and deliver training and documentation.
• Collaborate with colleagues who specialize in circuit simulation, cell characterization, FPGA timing models, and reliability methodologies.
• Set technical direction and mentor engineers on timing methodology.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field.
• Significant hands-on experience developing and deploying production design automation or timing flows.
• Experience with Static Timing Analysis (STA) and timing sign-off methodology, including timing constraints, multi-corner multi-mode (MCMM) analysis, crosstalk, OCV, timing derates, and advanced process-node timing challenges.
• Advanced experience with cell characterization and Liberty model generation, including LVF, POCV, statistical timing, or related variation-aware modeling methodologies.
• Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows.
• Experience with FPGA timing models, timing collateral, or customer-facing timing deliverables.
• Experience with timing reliability, aging, derating, electromigration, or other reliability-aware timing methodologies.
• Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off requirements.
• Experience evaluating, deploying, and influencing roadmaps for major commercial EDA tools and vendors, including the ability to identify tool gaps and drive technical escalations.
• Experience applying AI/ML techniques to design automation, including runtime/resource prediction, timing optimization, corner reduction, knowledge capture, or automated debug.
• Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives across multiple engineering organizations.

Salary Range

The salary range for this position in the Bay Area, California is $187,000 - $270,000 USD. Actual salary may vary based on a variety of factors including job location, performance, and experience.