Senior Staff Verification Engineer - PCIe & Memory Subsystems

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge data processing silicon platforms for AI, accelerated computing, cloud data center, and telecom customers. The group focuses on delivering innovative technology in diverse fast-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low-power techniques.

What You Can Expect

In this role, you will architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers, and contribute to the methodology behind such development.

Activities may include:

• Writing a verification test plan that employs random techniques, directed testing, and coverage analysis to thoroughly check functional correctness and performance.
• Developing a testbench using UVM, System Verilog, C/C++, and DPI.
• Verification at different levels of hierarchy, including block/unit, subsystem, and SOC levels.
• Working closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues.
• Expertise in PCIe and Memory Subsystems is highly desirable.

What We're Looking For

• BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering.
• 5–10 years of relevant professional experience.
• Background in creating test plans and designing test bench architectures that are hierarchical, reusable, and scalable.
• Background in SOC verification and test bench development using UVM and System Verilog, object-oriented programming, and constrained random methods.
• Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
• Other skills: effective communication and teamwork; high quality and attention to detail; independent learner, proactive in problem-solving.

Expected Base Pay Range (USD)

134,390 – 201,300 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation And Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage—from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and recognition and service awards to celebrate contributions and milestones.