Senior Staff Digital Design Engineer

About the Role

Impinj is a leading RAIN RFID provider and Internet of Things pioneer, inventing ways to connect everyday items to the Internet—including retail apparel, healthcare items, automobile parts, airline baggage, food, and more. With over 100 billion items connected and multiple Fortune 500 enterprises using our platform, we solve for a better understanding of our world. Join Impinj and help realize our vision of a boundless IoT, connecting trillions of everyday items.

The RAIN Reader IC (RIC) design group within Impinj Silicon Engineering is responsible for developing Impinj’s RIC products. The digital team owns the digital subsystems of these products, including the digital modem, microcontroller subsystem, digital control loops, calibration engines, and control/interface logic for analog IP. The team carries designs from architecture and micro-architecture definition through RTL, verification, DFT, timing closure, tapeout, post-silicon bring-up, and validation, partnering closely with chip architects, RF/analog designers, physical design, and CAD/EDA engineers.

Responsibilities

• Drive the digital design of Impinj's next-generation RAIN RFID Reader ICs from architecture through tapeout and silicon validation.
• Develop micro-architectures, create executable models, and implement RTL for complex digital and mixed-signal IC subsystems.
• Collaborate with chip architects and RF/analog engineers to partition and realize advanced mixed-signal architectures, including digital control loops, calibration engines, and interface logic for analog IP.
• Partner with physical design and verification teams to ensure timing closure, signal integrity, and delivery of production-ready Reader ICs.
• Define and implement DFT strategies—including scan insertion, BIST, and boundary scan—appropriate for mixed-signal Reader IC designs.
• Work with CAD/EDA engineers to evolve Impinj's ASIC/SoC design flows, methodologies, and best practices.
• Enhance existing RAIN RFID Reader products with new features, performance improvements, and power optimizations.
• Support post-silicon bring-up and debug, correlating RTL and simulation results with lab measurements to validate design intent.

Requirements

• Bachelor’s degree in Computer Engineering, with 12 years of experience (or 8 years with an MS or 5 years with a PhD).
• 12+ years of RTL design experience, including at least 2–3 full tapeout cycles, preferably on mixed-signal or RF-integrated ICs.
• Strong skills in digital logic design, micro-architecture definition, synthesis, and timing closure.
• Proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification.
• Solid understanding of digital design methodologies, including CDC analysis, clock gating, low-power design (UPF/CPF), and static timing analysis.
• Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT implementation (scan, MBIST, ATPG).
• Scripting proficiency in Python, Perl, or UNIX shell for flow automation and design productivity.
• Proven ability to lead technical workstreams, mentor junior engineers, and communicate effectively across analog, digital, and systems disciplines.

Benefits

• Competitive healthcare benefits and 401(k) plan with company match.
• Open paid time-off policy with respect for work/life balance.
• Eligibility for merit increases, annual bonus, and stock awards based on individual performance.
• Opportunity to earn sales incentives based on revenue or utilization for certain roles.
• Weekly Q&A sessions with the executive team.
• Collaborative and innovative work environment with a focus on teamwork and celebration of accomplishments.

US-based employees have access to a comprehensive list of benefits. The typical base pay range for this role across the US is $158,700 - $238,100, with individual pay determined by complexity, responsibilities, relevant experience, and skills.

Work Environment

Impinj’s headquarters is located in Seattle, offering spectacular views of the Olympics, Lake Union, and Mt. Baker, with a rooftop deck for enjoyment. The Brazilian site is in Porto Alegre, Rio Grande do Sul state, at Tecnopuc, a technology park providing a dynamic workplace for groundbreaking technologies.

This position may require access to technologies or data subject to U.S. export control regulations. Additional documentation related to national identity may be required to comply with these laws.