Senior SerDes Architect and Lead

About the role

SerDes architect and development lead focused on PAM4 ADC and DAC based wireline technologies. The successful candidate will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Omni Design is a young, fast‑growing, cutting‑edge technology company that values self‑motivation, initiative, leadership, teamwork, diversity, and excellence, and seeks trailblazers to bring its vision to fruition.

Responsibilities

• Work with customers to understand requirements.
• Lead development of high‑performance transistor‑level design from spec through design, layout supervision, silicon evaluation, characterization, and product introduction.

Qualifications

• 10+ years of experience in high‑performance analog or mixed‑signal IC development in advanced CMOS processes.
• Thorough familiarity with high‑speed PAM4 architectures and topologies.
• Experience designing high performance building block circuits such as bandgap reference, op‑amp, comparators, oscillators, DLL, PLL, CTLEs, CDRs, etc.
• Thorough understanding of equalization techniques (both analog and digital).
• Track record of successfully taking designs to production.
• Ability to work with customers to define products that address needs.
• Experience evaluating silicon on bench and familiarity with standard lab equipment.
• Strong intuitive and analytical understanding of transistor‑level circuit design including noise and mismatch analysis.
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks.
• Familiar with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE circuit simulation tools.
• MATLAB understanding preferred but not mandatory.
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process.
• Familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes.
• Ability to work independently, create and adhere to schedules.
• Strong written and verbal communication skills with ability to work with teams spread across geographic locations.
• Proactive in seeking help and sharing knowledge.