Senior RTL Design Engineer – DDR/LPDDR Memory Controller

About the role

We are seeking an experienced RTL Design Engineer to join our Memory Controller Design team. The ideal candidate will contribute to the development of advanced technologies and help deliver high-quality products to market.

Responsibilities

• Work closely with architects to define and implement IP microarchitecture features
• Develop RTL designs for IP features
• Analyze and optimize designs for power, performance, and area
• Participate in design specification reviews and code reviews
• Perform lint, CDC, and timing analysis to support high-quality design implementation
• Collaborate with verification engineers to validate and debug IP throughout the project lifecycle

Qualifications

• You have experience or interest in processor architecture, digital design, and verification
• You collaborate effectively with engineers across global teams and communicate technical concepts clearly
• You enjoy analyzing technical challenges, developing solutions, and continuously expanding your skills in a dynamic engineering environment

Preferred Qualifications:

• Experience with digital logic design
• Experience with Verilog and/or SystemVerilog
• Experience with scripting languages such as Python, Perl, or Tcl
• Understanding of computer architecture
• Experience with DDR or LPDDR memory systems
• Experience with EDA tools and design flows, including simulation, lint, and synthesis
• Experience with digital logic verification

Key Skills:

• Ability to work independently and collaboratively to deliver technical solutions
• Strong written and verbal communication skills
• Able to analyze technical problems and develop effective solutions

Requirements

• Bachelor’s or master’s degree in computer engineering, Electrical Engineering, Computer Science, or a related technical field

Benefits

Details about the benefits package are provided in the post.