Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

About the role

The Senior / Principal Layout Engineer will lead the exploration of next-generation memory modules and interconnects, driving architectural decisions through layout-driven insights and modeling-informed design. This role operates within the Module Architecture Group, focusing on pre-product definition, feasibility studies, and design tradeoff exploration.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects
• Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets
• Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy)
• Collaborate closely with SI/PI teams to co-optimize: Channel topology (fly-by, point-to-point, multi-drop evolution), Loss, reflection, and crosstalk mitigation strategies
• Return path integrity and reference plane design
• Define and influence SI/PI budgets at the module level
• Drive adoption of next-generation PCB technologies, including: Ultra-low-loss materials, Advanced HDI (microvias, stacked vias, via-in-pad), Hybrid bonding / advanced packaging integration (where applicable)
• Help develop next-gen layout methodologies and constraints for >10–20+ Gb/s signaling
• Help define: Routing rules for extreme speed interfaces, Skew/jitter budgets translated into physical constraints, Reference design guidelines for future programs
• Establish design rules that bridge architecture → SI/PI → layout → manufacturing
• Drive design reviews, risk assessments, and trade-off analysis
• Influence JEDEC and industry standards through practical layout feasibility input
• Mentor junior engineers and shape layout best practices across the organization

Requirements

• Bachelor’s degree in Electrical Engineering or related field
• 8–15+ years of experience in high-speed PCB layout
• Deep expertise in DDR/LPDDR memory interfaces or similar ultra-high-speed parallel interfaces
• Strong understanding of Signal Integrity (transmission lines, discontinuities, channel loss mechanisms) and Power Integrity (PDN design, target impedance, decoupling optimization)
• Advanced proficiency with Cadence Allegro / OrCAD (or equivalent high-end layout tools)
• Proven ability to influence architecture decisions through physical design constraints
• Experience working in cross-functional architecture or pathfinding environments
• Proficient in using AI tools in daily job

Additional Information

The US base salary range that Micron Technology estimates it could pay for this full-time position is: $202,000.00 - $344,000.00 a year. Additional compensation may include benefits, bonuses, and equity.