Senior Principal Hardware Applications Engineer

Key Responsibilities

• Lead SI/PI engineering activities for high-speed Ethernet switch and AI infrastructure platforms
• Define high-speed layout, routing, stack-up, and design guidelines for SerDes channels, power delivery networks, and sensitive interfaces
• Perform channel modeling, post-layout extraction, simulation, and analysis to identify and resolve design issues
• Conduct SI/PI design reviews and provide recommendations to improve performance and design margins
• Support high-speed SerDes technologies, including 112G and 224G PAM4, and contribute to future 448G platform development
• Lead compliance testing, lab characterization, and hardware debugging using tools such as VNAs, BERTs, oscilloscopes, TDRs, and jitter analyzers
• Provide SerDes tuning and design guidance based on simulation results, lab measurements, and field data
• Work closely with customers, ODMs, silicon teams, hardware engineers, software teams, and operations teams
• Support reference design development, customer platform bring-up, qualification, and production ramp
• Develop and deliver SI/PI training for customers, ODM partners, and internal engineering teams
• Mentor engineers and provide technical leadership across strategic customer programs
• Contribute SI/PI expertise to future product architecture and technology roadmap discussions
• Travel to customer sites, ODM locations, and labs as needed

Required Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field
• 15+ years of experience in high-speed hardware design, development, or validation
• 10+ years of hands-on Signal Integrity (SI) and Power Integrity (PI) experience with high-speed SerDes platforms
• Strong knowledge of 25G NRZ, 112G, and 224G PAM4 technologies
• Experience with SI/PI channel modeling, PCB layout, stack-up design, simulation, compliance testing, and SerDes tuning
• Strong understanding of PDN analysis, including impedance, IR drop, decoupling, transient response, and voltage droop
• Experience with SI/PI tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or similar tools
• Hands-on experience with high-speed lab and test equipment, including VNAs, BERTs, oscilloscopes, TDRs, and jitter analyzers
• Strong customer-facing, technical leadership, communication, and problem-solving skills
• Experience providing technical guidance or training to engineering teams

Pay

USD $1,99,800 – $2,66,400 / yr

Schedule

100% Onsite