Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization

Key Responsibilities

• Define and drive the technical roadmap for timing analysis, timing modeling, and timing optimization within the Quartus FPGA Compiler.
• Lead the design and implementation of advanced timing engines supporting FPGA compilation, placement, routing, and timing closure.
• Develop methodologies to improve timing convergence across the Quartus RTL-to-bitstream flow.
• Partner with architecture and compiler teams to enable best-in-class timing QoR and signoff correlation.
• Architect and develop next-generation STA capabilities, including graph-based and path-based timing analysis.
• Advance support for complex timing scenarios, such as: Multi-corner, multi-mode (MCMM) analysis, timing exception handling, clock domain crossing analysis, variation-aware timing methodologies, and incremental timing analysis.
• Improve timing accuracy while maintaining industry-leading scalability and runtime performance.
• Develop timing modeling methodologies that accurately correlate Quartus results with silicon behavior and signoff requirements.
• Drive innovations in delay modeling, clock modeling, timing abstraction, and hierarchical timing analysis.
• Partner with FPGA architecture teams to ensure accurate representation of device resources and timing characteristics.
• Design scalable data structures and algorithms for timing analysis and optimization.
• Improve compiler performance through parallelization, multi-threading, and incremental processing techniques.
• Drive architectural improvements that enable efficient handling of large, complex FPGA designs.
• Provide technical mentorship and thought leadership across engineering teams.
• Collaborate with synthesis, placement, routing, architecture, verification, and software engineering organizations.
• Influence future FPGA compiler capabilities through technical strategy, innovation, and long-term planning.

Qualifications

• MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field.
• 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
• Deep expertise in: Static Timing Analysis (STA), timing closure methodologies, timing modeling and correlation, physical design optimization, RTL-to-GDS or RTL-to-bitstream design flows, multi-corner multi-mode (MCMM) analysis.
• Strong understanding of: Placement and routing algorithms, clock analysis and optimization, Path-Based Analysis (PBA), constraint management and timing exceptions, incremental timing architectures.
• Extensive software development experience in C++ and large-scale optimization systems.
• Proven track record developing high-performance, highly scalable EDA engines.

Preferred Qualifications

• Direct experience developing FPGA compilation tools.
• Prior experience with the Quartus compiler, Timing Analyzer, Fitter, Routing, or related FPGA implementation technologies.
• Expertise in one or more of the following: Path-based timing optimization, Clock-Reconvergence Pessimism Removal (CRPR), Latch-based timing analysis, Incremental optimization frameworks, Timing-driven placement and routing, Variation-aware analysis techniques.
• Experience designing multi-threaded or distributed EDA infrastructure.
• Industry-recognized technical leadership demonstrated through patents, publications, standards contributions, or major product innovations.