Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.

About the Role

Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior experienced technical leader to serve as Hardware Chip Lead on our next-generation ODSP programs.

Responsibilities

• Serve as the primary hardware technical owner for an ODSP chip program, responsible for tracking and driving progress across all hardware design phases from POR (Plan of Record) through MPR (Mass Production).
• Finalize the Product Requirements Document (PRD) and bring-up requirements in collaboration with architecture, marketing, and applications engineering teams.
• Represent hardware engineering at all key program milestones: Pre-PA, PA, PSM, POR, Design Reviews, Tape-Out, and MPR.
• Coordinate and align cross-functional teams including analog design, digital design, DV, DFT, physical design, STA, firmware, validation, ATE/test engineering, product engineering, and quality.
• Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence.
• Provide technical leadership for the full chip design, independently proposing and defining high-level technical solutions across the hardware stack.
• Set technical direction and drive resolution of complex, cross-disciplinary design challenges spanning analog/digital integration, high-speed SerDes, DSP datapath, and SoC architecture.
• Proactively identify technical risks early in the design cycle and drive mitigation strategies across functional teams.
• Take an active role in setting and prioritizing BU milestones and objectives; participate in architecture and design reviews at the chip and block level.
• Drive continuous improvement in design methodology, flows, and quality across the ODSP hardware organization.
• Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), including architecture, RTL, physical design, DFT, timing closure, and tape-out.
• Own the chip bring-up plan and execution, coordinating multi-site teams across global locations; drive Phase 0, Phase 1, and Phase 2 bring-up activities through to silicon validation.
• Oversee silicon validation, PVT characterization, ATE test program development, qualification (ESD, LU, HTOL), and production release.
• Drive resolution of post-silicon issues, coordinating debug across analog, digital, firmware, and validation teams.
• Ensure all hardware deliverables — including PRD, design documentation, and bring-up requirements — are complete and on schedule.
• Mentor and develop engineers across the ODSP hardware organization; invest in building technical depth and breadth within the team.
• Foster a culture of knowledge sharing, technical rigor, and continuous learning.
• Coach and develop engineering talent; provide guidance and feedback to support career growth at all levels.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience OR Master’s degree in Electrical Engineering, Computer Engineering, or related field with 10–12 years of experience OR PhD in Electrical Engineering, Computer Engineering, or related field with 8–10 years of experience.
• Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization.
• Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm).
• Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out.
• Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines.
• Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams.
• Experience with ATE test program development, silicon characterization, qualification (HTOL, ESD, LU), and production release.
• Excellent communication, interpersonal, and presentation skills; ability to represent hardware engineering to BU leadership and cross-functional stakeholders.
• Highly motivated, self-driven, and able to manage ambiguity in a fast-paced, multi-program environment.

Preferred Skills

• Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products.
• Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems.
• Knowledge of SiPho (Silicon Photonics) integration and module-level validation.
• Experience working in a multi-site, globally distributed engineering organization.

Pay

Expected Base Pay Range (USD): $182,360 - $273,200 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage — from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include:

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.