Senior Principal DFT Design Engineer

About the role

Cadence is seeking a SoC/ASIC Digital Design Engineer with expertise in Design for Test (DFT) to join our team of leaders and innovators making an impact on the world of technology.

Responsibilities

• Implement scan chain insertion and compression scan technologies
• Develop and apply memory built-in self-test (MBIST) solutions
• Generate ATPG patterns following systematic quality metrics to achieve design test coverage goals
• Debug and analyze failures to improve fault coverage
• Verify ATPG testbenches and debug root causes of simulation mis-compares
• Work with JTAG 1149.1/6, IEEE1500, and IEEE1687 standards
• Collaborate with cross-functional teams including Architecture, Design, and internal/external customers
• Complete DFT tasks independently in a fast-paced project environment

Requirements

• 10–20 years of professional experience in SoC/ASIC Digital Design with a focus on Design for Test (DFT)
• Intimate knowledge of DFT insertion flows and basic scan chain insertion using synthesis or other software tools
• Experience with compression scan insertion, LBIST, and other scan technologies
• Expertise in memory built-in self-test (MBIST)
• Proven ability in Automatic Test Pattern Generation (ATPG) to meet design test coverage goals
• Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687
• Strong problem-solving skills with a disciplined, thorough, and methodical approach
• Ability to work collaboratively in a team environment and with cross-functional stakeholders
• Self-driven and committed to working in a fast-paced project environment

Qualifications

• Hands-on knowledge of synthesis, verification, and debugging Verilog testbenches (highly desirable)
• Prior experience with Cadence tools and flows (highly desirable)
• Knowledge of timing analysis and equivalency checks (added bonus)
• US citizenship preferred