Senior Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

About the role

AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production.

Responsibilities

• Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
• Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
• Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
• Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
• Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams
• Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability

Qualifications

• 6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
• Experience as a mentor, tech lead or leading an engineering team
• 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
• Experience programming in C++, using advanced language features
• Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Benefits

No benefits provided as per the job posting.

Pay

Base salary range: $168,100.00 - $227,400.00 USD annually

Schedule

Full-time