Senior Physical Design Engineer

About the role

NVIDIA is seeking a Senior Physical Design Engineer to join our dynamic team. With a rich history of innovation, NVIDIA has been at the forefront of technological advancements, including the development of GPUs, AI, and more. This role involves leading the physical design and implementation of GPU and other ASICs for various markets.

Responsibilities

• Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
• Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
• Craft designs for static timing analysis, power and noise analysis and back-end verification.

Requirements

• BSEE (MSEE preferred) or equivalent experience.
• 8+ years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology.
• Your successful track record of delivering designs to production is a requirement.
• Shown experience in the following areas: Power, Performance and Area improvement Initiatives is a plus.
• Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics.
• Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs.
• Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
• Strong analytical and debugging skills required.
• Proficiency using Python, Perl, Tcl, Make scripting is helpful.

Qualifications

• BSEE (MSEE preferred) or equivalent experience.
• 8+ years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology.
• Your successful track record of delivering designs to production is a requirement.
• Shown experience in the following areas: Power, Performance and Area improvement Initiatives is a plus.
• Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics.
• Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs.
• Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
• Strong analytical and debugging skills required.
• Proficiency using Python, Perl, Tcl, Make scripting is helpful.

Skills

• Power, Performance and Area improvement Initiatives.
• P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics.
• Custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs.
• Timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
• Python, Perl, Tcl, Make scripting.

Benefits

• NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers.
• We have some of the most forward-thinking and hardworking people in the world working for us.
• If you're creative and autonomous, we want to hear from you.

Pay

• The base salary range is $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5.

Schedule

• Applications for this job will be accepted at least until May 18, 2026.

Company Information

• NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.
• We highly value diversity in our current and future employees, and we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.