Senior Physical Design Engineer
NVIDIA · Westford, MA · 5 days ago
EngineeringFull-time
About the role
NVIDIA is seeking a Senior Physical Design Engineer to join our Networking Silicon engineering team. The ideal candidate will be responsible for leading all aspects of physical design and implementation of System On Chip (SOC) devices targeting networking markets. This role involves working at the partition and chiplet levels, participating in the establishment of physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, and placement and routing (P&R).
Responsibilities
- Lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
- Work at the partition and chiplet level.
- Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
- Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
Requirements
- BSEE / MSEE or equivalent experience.
- 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
- A successful track record of delivering designs to production is a requirement.
- Able to assist in design flow development and debugging, including application of ML/AI solutions.
- Already a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
- Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
- Strong analytical and debugging skills.
- Proficiency using Python, Perl, Tcl, Make scripting is helpful.
- Great teammate.
Qualifications
- BSEE / MSEE or equivalent experience.
- 5 years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
- A successful track record of delivering designs to production is a requirement.
- Able to assist in design flow development and debugging, including application of ML/AI solutions.
- Already a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
- Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
- Strong analytical and debugging skills.
- Proficiency using Python, Perl, Tcl, Make scripting is helpful.
Skills
- Strong analytical and debugging skills.
- Proficiency using Python, Perl, Tcl, Make scripting is helpful.
Benefits
- Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.
- Eligible for equity and benefits.
Pay
- Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.
Schedule
- Not specified.
Benefits
- Not specified.
Company Information
- NVIDIA is widely considered to be the leader in AI computing and one of the technology world's most desirable employers.
- We have some of the most creative and hardworking people in the world working for us.
- We are committed to fostering an inclusive work environment and are proud to be an equal opportunity employer.
Contact Information
- Applications for this job will be accepted at least until July 13, 2026.