Senior Physical Design and Timing Engineer

About the role

NVIDIA is seeking a Senior Physical Design and Timing Engineer to join our dynamic and growing team. This role involves driving physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs, and SoCs at various levels. Responsibilities include frontend and backend implementation from RTL to GDS2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. The position requires interaction with multiple teams and applying knowledge to improve convergence flows working with the Methodology Team.

Responsibilities

• Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Work in a cross-functional environment interacting with multiple teams.
• Apply knowledge and experience to improve the convergence flows working with the Methodology Team.

Requirements

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 3+ years experience in Synthesis and Timing.
• Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Experience in critical path planning and crafting needed.
• Hands on experience in logic synthesis and equivalence checking/FV.
• Good understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
• Understanding of DFT logic and hands-on experience in design closure.
• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.
• Knowledge in process variation effect modeling and experience in design convergence taking into account variations.
• Expertise and in-depth knowledge of industry standard EDA tools.
• Proficiency in programming and scripting languages, such as, Perl, Tcl, Make, Python, etc.

Qualifications

• Background in high-performance design, such as CPU, GPU, LPU, implementation and timing convergence, is a plus.
• Experience with DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.
• Experience in methodology and/or flow development/automation.

Skills

• Strong understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.
• Knowledge in process variation effect modeling and experience in design convergence taking into account variations.
• Expertise and in-depth knowledge of industry standard EDA tools.
• Proficiency in programming and scripting languages, such as, Perl, Tcl, Make, Python, etc.

Benefits

NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family here. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4. You will also be eligible for equity and benefits.

Pay

$136,000 - $218,500 for Level 3
$168,000 - $264,500 for Level 4

Schedule

Full-time