Senior Physical Design and Timing Engineer

About the Role

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we're tapping into the unlimited potential of AI to define the next era of computing—an era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team.

What You'll Be Doing

• Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level
• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation
• Work in a cross-functional environment interacting with multiple teams

What We Need To See

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 3+ years of experience in physical design, synthesis, and timing
• Strong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs
• Demonstrated success improving power, performance, and area through design improvements, critical-path planning and crafting, or methodology/workflow improvements
• Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk
• Expertise and in-depth knowledge of industry-standard EDA tools
• Proficiency in Python, Tcl, Perl, Make, or similar scripting languages as well as AI/ML/DL/LLMs

Ways To Stand Out From The Crowd

• Physical design experience on high-performance CPUs, GPUs, LPUs, or AI accelerator designs
• Expertise or innovation in advanced physical design & circuits optimizations, clocking, or timing-closure strategies
• Experience in developing scalable optimization and signoff solutions through automation or AI/Agentic framework

Pay

Base salary range: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.