Senior Photonic Layout Design Engineer

About the role

NVIDIA is seeking a Senior Photonic Layout Design Engineer to join a growing group responsible for handling high-speed mixed-signal & Silicon Photonic Designs. You will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness. You will work within a highly collaborative, multidisciplinary team of photonics, CMOS, packaging, and systems engineers to drive next-generation Silicon Photonics (SiPh) and SERDES products.

Responsibilities

• Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
• Verification & Mitigation: Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
• Test Vehicle & Component Development: Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows.
• Automation & AI-Assisted Workflows: Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows.

Requirements

• BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience).
• At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
• Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
• Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield).
• Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows.
• Ability to optimize workflows using best-known methods (BKMs), and proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals.

Pay

Base salary range: 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5. You will also be eligible for equity and benefits.