Senior IC Packaging Engineer

About the role

Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging.

Own C4 bumping process flows — UBM deposition, solder bump plating or ball drop, reflow, and flux clean — for flip-chip and 3D-IC applications.

Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules.

Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes.

Support new product/technology introduction (NPI) from pathfinding through HVM transfer.

Mentor junior engineers and contribute to internal process documentation and best-practice standards.

Responsibilities

• Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging.
• Own C4 bumping process flows — UBM deposition, solder bump plating or ball drop, reflow, and flux clean — for flip-chip and 3D-IC applications.
• Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules.
• Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes.
• Support new product/technology introduction (NPI) from pathfinding through HVM transfer.
• Mentor junior engineers and contribute to internal process documentation and best-practice standards.

Requirements

• MS/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field.
• 5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering - working with major OSAT’s (ASE, AMKOR, SpiL etc).
• An extensive personal network within key OSATs would be very advantageous.
• Direct, hands-on experience with TSV reveal (grinding, CMP, dielectric reveal, thickness metrology) and C4 bumping (UBM, electroplating or solder ball attach, reflow).
• Strong understanding of 2.5D/3D packaging architectures (interposers, chiplets, HBM integration, hybrid bonding is a plus).
• Deep understanding of semiconductor device physics, packaging materials, and thermal/mechanical analysis.
• Experience with statistical process control, DOE methodology, and yield analysis.
• Familiarity with metrology and inspection tools relevant to bumping/TSV (CD-SEM, AFM, profilometers, X-ray, AOI/SEM defect review).
• Working knowledge of cleanroom fab operations and contamination control.
• Excellent cross-functional communication skills; comfortable working with equipment OEMs and multi-site teams.

Preferred Qualifications

• Experience with copper pillar bumping, micro-bump, or hybrid bonding processes.
• Background in wafer thinning and temporary bonding/debonding for advanced node packaging.
• Exposure to reliability testing (thermal cycling, electromigration, HAST) for packaged parts.
• Experience supporting HVM ramp in an OSAT or IDM environment.