Senior Hardware Design Engineer (Teradyne, Tualatin, OR)
Teradyne · Tualatin, OR · 2 wk ago
Engineering$141k–$226k/yrFull-time
About the role
You will join a group of dedicated, enthusiastic, and dynamic team players in the ‘Memory Tester’ Business Unit. Here, we design IC testers for the DRAM and FLASH memory market.
Responsibilities
- Concept-through-production design of analog and digital instruments for automated test equipment
- Investigate customer-reported problems for root cause analysis
- Implement improvements in design, test, and/or operations
Requirements
- 10+ years of experience as a circuit design engineer, with experience designing digital and analog board-level circuitry
- Experience with Op-Amps, analog designs, filters, stability, compensation networks, control loops
- Working familiarity with High-Speed Design techniques
- Candidate should be very familiar with switching power supply design, and related noise, crosstalk issues on multi-layer PCBs
- Knowledge of Thermal & Mechanical fundamentals
- Relevant PCB layout experience to guide CAD personnel
- Experience with circuit simulation tools (e.g., SPICE, ADS, Ansys)
Qualifications
- BSEE, MSEE or equivalent
Skills
- Strong communications skills
- Ability to work with geographically dispersed multifunctional teams
- Desire to take on project leadership
- Proven ability to lead junior engineers
- Self-Starter
- Desire to work as a team with a results-driven approach
- Strong problem-solving and reasoning skills
Benefits
Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.
Pay
The base salary range for this role is $141,400 - $226,200. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.
Schedule
N/A