Senior Hardware Acceleration Efficiency Architect

Benchmarks and Workload Optimization

• Benchmark emulation and FPGA workloads to quantify performance and utilization baselines.
• Track improvements over time in system availability and job throughput.

Scheduling and Resource Management

• Optimize scheduling, queuing, and recovery mechanisms to improve system availability.
• Integrate with EDA vendor APIs to automate resource management and streamline job orchestration.

Automation and Workflow Optimization

• Develop data pipelines and performance dashboards to visualize trends and guide tuning efforts.
• Drive continuous improvement through automation and workflow optimization.

Collaboration and Continuous Improvement

• Partner with EDA tool vendors to validate and deploy performance enhancements in production workloads.
• Collaborate with Arm’s in-house scheduler team to enhance scheduling intelligence and resource allocation.

Technical Skills and Experience

• Strong (minimum 5 years) experience in hardware emulation and FPGA environments.
• Proven ability to benchmark and profile emulation workloads, interpret performance data, and drive targeted improvements.
• Understanding of emulation and FPGA prototyping workflows, including model build, compile, partitioning, mapping, execution, debug, and regression usage patterns.
• Experience integrating vendor APIs or SDKs into custom automation or monitoring solutions.
• Familiarity with scheduler design and integration.
• Proficiency in Linux-based environments and scripting (Python, Bash) for automation and analysis.
• Strong analytical mentality with a data-driven, test-based approach to performance validation.
• Familiarity with Prometheus, Grafana, or similar metrics frameworks for system visibility.

Nice to Have

• Experience building workflow orchestration or monitoring tools for large-scale verification environments.
• Exposure to cloud-hosted emulation or elastic compute models.
• Knowledge of EDA tool internals and licensing mechanisms.
• Experience collaborating with EDA vendors on joint optimization or benchmarking initiatives.