Senior FPGA Verification Engineer
for section headings. Use - for any list of duties/requirements/benefits. Use
for prose.
We need to preserve all substantive information, not invent or summarize away detail. Remove boilerplate, duplicated lines, application instructions. Also remove cookie/navigation/legal/EEO/equal-opportunity/scam-warning boilerplate, duplicated lines, and application instructions. So we must remove the "Protecting Yourself from Recruitment Scams" and "Data Privacy" sections entirely. Also remove the line "US Salary Range $191,000—$253,000 USD" maybe we keep as part of Pay section? The instruction: include a section ONLY when the posting has real, specific content for it — never emit a heading followed by filler/placeholder text (e.g. "commensurate with experience", "not specified", "N/A", "varies", "TBD") and never create Pay/Schedule/Benefits sections unless the posting actually states them. The posting states "US Salary Range $191,000—$253,000 USD". That's specific, so we can include a Pay section with that content. Also Benefits: they have a paragraph describing benefits. So we can include Benefits section.
We must not include schedule because not mentioned.
We need to avoid duplication: there is duplicate line "experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment." appears twice. We should keep only one instance.
Also "Required Qualifications" includes bullet-like sentences; we can turn them into
- . Similarly "Preferred Qualifications". Also "What You’ll Do" list.
We need to preserve all substantive info: The company description at start: "Anduril Industries is a defense technology company..." That's about the company; maybe we can include as a brief intro paragraph before sections? The instruction: do NOT repeat the job title as a heading (the page already shows it) and do NOT put Job ID / requisition numbers as headings — fold minor metadata into a short
or drop it. The intro about Anduril could be considered company overview; we can keep as a
before sections.
Also "About The Team" and "About The Job" sections: we can combine? They are separate headings but we can treat them as sections with
. The instruction: use for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). They gave examples but we can use any heading that matches content. So we can have About the Team
, About the Job
, What You’ll Do
, Required Qualifications
, Preferred Qualifications
, Pay
, Benefits
. Ensure we don't create empty sections.
We need to output only HTML fragment, no /, no markdown fences.
Let's craft.
First paragraph: company overview: "Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years."
Then About the Team
with paragraph: "The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage."
Then About the Job
with paragraph: "The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products."
Then What You’ll Do
with - items:
- Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
- Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
- Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
- Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
- Contribute to engineering estimates for new program pursuits.
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
Make sure each
- ends with period? Keep as is.
Then
Required Qualifications
with - items:
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Note: we removed duplicate line.
Then
Preferred Qualifications
with - items:
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
Then
Pay
with paragraph: "US Salary Range $191,000—$253,000 USD". Could also note that actual salary offer may vary based on experience etc. The posting includes a sentence: "The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations." That's substantive; we should include it. So we can put that as paragraph after the range.
Thus Pay
with containing both lines.
Then
Benefits
with paragraph: The benefits description: "Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including: At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits."
We need to preserve all substantive info; we can keep as paragraph.
Make sure not to include the "Explore Our Benefits" link? It's just text; we can keep.
We must not include any boilerplate like scam warnings, data privacy, etc.
Now produce HTML.
Check for any duplicate content: we removed duplicate line.
Check for any leftover boilerplate: The "US Salary Range $191,000—$253,000 USD Benefits The salary range for this role is an estimate..." originally had "Benefits" after salary range but we separated.
We need to ensure we didn't inadvertently include "Benefits" heading inside Pay section. We'll separate.
Now produce final HTML.
Let's craft:
Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
About the Team
The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.
About the Job
The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.
What You’ll Do
- Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
- Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
- Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
- Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
- Contribute to engineering estimates for new program pursuits.
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
Required Qualifications
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Preferred Qualifications
- Experience with ASIC/FPGA lab validation
for prose. We need to preserve all substantive information, not invent or summarize away detail. Remove boilerplate, duplicated lines, application instructions. Also remove cookie/navigation/legal/EEO/equal-opportunity/scam-warning boilerplate, duplicated lines, and application instructions. So we must remove the "Protecting Yourself from Recruitment Scams" and "Data Privacy" sections entirely. Also remove the line "US Salary Range $191,000—$253,000 USD" maybe we keep as part of Pay section? The instruction: include a section ONLY when the posting has real, specific content for it — never emit a heading followed by filler/placeholder text (e.g. "commensurate with experience", "not specified", "N/A", "varies", "TBD") and never create Pay/Schedule/Benefits sections unless the posting actually states them. The posting states "US Salary Range $191,000—$253,000 USD". That's specific, so we can include a Pay section with that content. Also Benefits: they have a paragraph describing benefits. So we can include Benefits section. We must not include schedule because not mentioned. We need to avoid duplication: there is duplicate line "experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment." appears twice. We should keep only one instance. Also "Required Qualifications" includes bullet-like sentences; we can turn them into
- . Similarly "Preferred Qualifications". Also "What You’ll Do" list.
We need to preserve all substantive info: The company description at start: "Anduril Industries is a defense technology company..." That's about the company; maybe we can include as a brief intro paragraph before sections? The instruction: do NOT repeat the job title as a heading (the page already shows it) and do NOT put Job ID / requisition numbers as headings — fold minor metadata into a short
or drop it. The intro about Anduril could be considered company overview; we can keep as a
before sections. Also "About The Team" and "About The Job" sections: we can combine? They are separate headings but we can treat them as sections with
. The instruction: use
for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). They gave examples but we can use any heading that matches content. So we can have
About the Team
,About the Job
,What You’ll Do
,Required Qualifications
,Preferred Qualifications
,Pay
,Benefits
. Ensure we don't create empty sections. We need to output only HTML fragment, no /, no markdown fences. Let's craft. First paragraph: company overview: "Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years." ThenAbout the Team
with paragraph: "The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage." ThenAbout the Job
with paragraph: "The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products." ThenWhat You’ll Do
with- items: - Verification environment architecture and design using tools like SystemVerilog or OVM/UVM - Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking - Testbench development for the verification of RTL blocks using VHDL or SystemVerilog - Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow - Contribute to engineering estimates for new program pursuits. - Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status Make sure each
- ends with period? Keep as is.
Then
Required Qualifications
with- items:
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Note: we removed duplicate line.
Then
Preferred Qualifications
with- items:
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
Then
Pay
with paragraph: "US Salary Range $191,000—$253,000 USD". Could also note that actual salary offer may vary based on experience etc. The posting includes a sentence: "The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations." That's substantive; we should include it. So we can put that as paragraph after the range. ThusPay
withcontaining both lines. Then
Benefits
with paragraph: The benefits description: "Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including: At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits." We need to preserve all substantive info; we can keep as paragraph. Make sure not to include the "Explore Our Benefits" link? It's just text; we can keep. We must not include any boilerplate like scam warnings, data privacy, etc. Now produce HTML. Check for any duplicate content: we removed duplicate line. Check for any leftover boilerplate: The "US Salary Range $191,000—$253,000 USD Benefits The salary range for this role is an estimate..." originally had "Benefits" after salary range but we separated. We need to ensure we didn't inadvertently include "Benefits" heading inside Pay section. We'll separate. Now produce final HTML. Let's craft:Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
About the Team
The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.
About the Job
The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.
What You’ll Do
- Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
- Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
- Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
- Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
- Contribute to engineering estimates for new program pursuits.
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
Required Qualifications
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Preferred Qualifications
- Experience with ASIC/FPGA lab validation
- items:
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
Then
- items:
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Note: we removed duplicate line.
Then