Senior Formal Verification Engineer (CH-64001149)

Responsibilities

• Develop and enhance formal methodologies to be rolled out to the wider design and verification teams and investigate new capabilities based on formal.
• Mentor engineers in formal verification, developing their talents and understanding of formal techniques and application of formal methodologies.
• Support, and where necessary coach, the verification team to follow, and improve, defined methodology practices.
• Develop test plans and verification methodologies to verify the microarchitecture and design.
• Perform failure analysis and resolution, coverage analysis, and population.
• Implement and improve functional verification.

Requirements

• Master's degree in Electrical or Computer Engineering with 8+ years or PhD in Electrical or Computer Engineering with 5 +years of formal verification experience.
• Proven expertise in designing and implementing formal verification environments for complex IP/module-level designs.
• Demonstrated ability to lead and drive the verification process from inception to completion.
• Excellent communication skills and a collaborative approach to working with team members.
• Proficiency in System Verilog, UVM, or equivalent methodologies.
• Familiarity with scripting languages such as Python, Perl, TCL, Bash.
• Expertise in formal property languages, with SVA knowledge.
• Experience in property-based model-checking.
• Knowledgeable in Signal Processing, analog and digital design fundamentals.