Senior Failure Analysis Engineer, Optical Fault Isolation

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

About the Role

We are seeking a highly skilled Senior Failure Analysis (FA) Engineer to drive die-level logic fault localization for our advanced semiconductor devices. You will work closely with our Design, Test, and DFT teams to identify root causes of silicon failures, accelerate yield improvements, and ensure the highest quality of our cutting-edge products.

Responsibilities

• Die-Level Logic Fault Localization: Perform complex, hands-on failure analysis and root cause identification using physical and electrical fault isolation methodologies.
• ATE Testing & Debugging: Utilize the Advantest 93K platform to test & characterize DUT and setup required test-looping to enable LVP, SDL and other FA techniques.
• DFT Collaboration: Leverage knowledge of Design for Test (DFT) basics—including Scan, BIST, and boundary scan—to interpret test patterns and guide fault isolation strategies.
• Root Cause Analysis: Analyze test results to distinguish between design, fab process, or tester-induced failures, delivering actionable corrective actions.
• Cross-Functional Leadership: Collaborate with Product Engineering, Test Engineering, and Foundry Engineering teams to resolve yield, performance, and reliability issues.

Requirements

• MS degree in Electrical Engineering, Materials Science, Physics, or a closely related field (or equivalent experience).
• 5+ years of direct, hands-on experience in semiconductor failure analysis, yield engineering, or product engineering.
• Strong practical experience with the Advantest 93k test platform.
• Good understanding of DFT basics and logic fault localization.
• Expert level experience on LFI techniques (LVP, EMMI, SDL, OBIRCH, or other photon/laser-based techniques).
• Bonus if you also have experience with Teradyne Ultraflex plus.
• Excellent problem-solving abilities, strong technical communication skills, and a proven track record of driving complex issues to resolution.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 144,000 USD - 230,000 USD for Level 4, and 168,000 USD - 264,500 USD for Level 5. You will also be eligible for equity and benefits.