Senior Engineer, Digital Design Engineering

Duties

• Develop state-of-the-art solutions involving analog, mixed-signal, power, RF, and digital signal processing integrated circuits used in electronic equipment for a wide-range of industries, including healthcare, communications, aerospace and defense, instrumentation, and emerging markets.
• Work with cross-functional teams, including analog design, systems design, firmware, applications, product engineering and ATE on product development through successful product execution.
• Participate in the entire product development lifecycle from definition to product release.
• Apply formal design and verification techniques to design and architect detailed verification plans.
• Perform simulation, debugging, code coverage, and gate level simulations.
• Work with design teams to resolve complex debugging and verification failures.
• Develop test plans and work with product, applications, and test engineers to ensure designs meet performance and testability goals.
• Write user guides to define software setup and operating procedures.
• Work with and run block and top-level test benches to verify modules and integration of designs.
• Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs.
• Document design work, present results, and participate in project meetings.

Requirements

• Must have a Master’s degree in Electrical Engineering, Electronic Engineering, Computer Science, Computer Engineering, or closely related technical field (willing to accept foreign education equivalent) and 24 months of experience as a Digital Design Engineer or related occupation performing digital or mixed signal design and verification.
• Must possess the following (quantitative experience requirements not applicable to this section):
• Demonstrated Expertise (DE) applying digital design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products.
• DE running simulations, synthesis, and CDC using Cadence or Synopsis tools.
• DE verifying integration and functionality of design utilizing verification tools and techniques, including Verilog, System Verilog, and overall ASIC design flow.
• DE working with verification plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
• DE participating in all phases of digital design development and tapeout activities (architecture, debug, gate level simulations, and evaluation).