Senior Director, SoC Design Verification
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem. This team will be responsible for delivering high-quality customer silicon for advanced AI, XPU, and XPU-Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next-generation compute platforms.
What Makes This Opportunity Unique
This is a rare foundational leadership opportunity - you'll shape design strategy from the ground up and build a world-class team as part of our strategic expansion into Southern California. You're not joining an established team—you're building one. You'll hire the engineers, define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design organization.
What You Can Expect
On-site role based in San Diego, where your leadership will be hands-on and collaborative as you establish our local presence.
Lead end-to-end verification execution for complex, multi-million gate SoCs with a zero-defect mindset—owning DV strategy, emulation planning, and post-silicon validation scope from architecture through production tapeout.
Build and scale a high-performance engineering team—you'll hire verification engineers, define team culture, mentor rising leaders, and create development programs that attract and retain top talent in the San Diego market.
Define verification methodologies and testbench architectures that set the standard for quality across CCSBU, evaluating and selecting tools, driving coverage-driven verification strategies, and monitoring industry trends to keep Marvell at the forefront.
Partner daily with Architecture, Design, DFT, Physical Design, Firmware, and System teams—you'll be in strategy sessions with architects, design reviews with RTL leads, and integration meetings with cross-functional leaders to ensure seamless product execution.
Drive continuous productivity improvements through both incremental optimizations and bold methodology changes—whether it's implementing new emulation strategies, automating coverage analysis, or adopting next-generation verification tools.
Own executive-level communication—you'll present verification status to senior leadership, define execution timelines with stakeholders, and make strategic decisions about resource allocation, tool investments, and team priorities.
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related field with 15+ years of professional experience OR Master's/PhD with 10+ years of experience in ASIC/SoC development.
Proven ability to lead ASIC development teams and deliver high-quality silicon—you've built teams before, hired top talent, and have a track record of successful tapeouts in advanced process nodes.
Deep understanding of SoC architecture, including processor cores, memory subsystems (DDR/HBM), high-speed interfaces (PCIe, Ethernet, NVMe), and complex IP integration.
Expert knowledge of DV methodologies—hands-on experience with UVM, SystemVerilog, constrained random verification, formal verification, coverage-driven strategies, and emulation/FPGA prototyping.
Strong cross-functional leadership and communication skills—you can influence without authority, present technical strategies to executives, and build trust across design, architecture, physical design, and firmware organizations.
Self-driven, curious, and highly motivated to learn new technologies, adapt to evolving methodologies, and tackle the industry's most challenging verification problems.
Expected Base Pay Range (USD)
$197,400 - $292,150, $ per annum
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
U.S. Export Control Compliance
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.