Senior Digital VLSI Design Engineer

About the role

We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be delivered to the SOC teams.

Responsibilities

• Define and enforce synchronization strategies across complex, multi-clock domains in advanced process nodes.
• Own the constraint creation process for synthesis, full-chip CDC/RDC methodology, establish rigorous constraints and waivers to ensure zero-defect silicon.
• Collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset-glitch issues before RTL freeze.
• Mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign-off for multi-site global teams.

Requirements

• BSEE required, MSEE/PHD preferred
• 8+ years of related experience

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

Broadcom offers a competitive and comprehensive benefits package:

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays, paid sick leave and vacation time

The company follows all applicable laws for Paid Family Leave and other leaves of absence.