Senior Digital Signal Processing Engineer

Department: Avionics Location: Redondo Beach Compensation: $145,000 - $185,000 / year Description We are seeking a highly skilled Senior DSP Engineer to lead the development, implementation, and verification of advanced signal-processing algorithms for high-performance communication systems as part of Impulse’s next generation of space vehicles. The ideal candidate will have strong theoretical DSP knowledge, practical fixed-point implementation experience, and hands-on hardware integration skills. Responsibilities Design, implement, and optimize DSP algorithms for advanced communication systemsDevelop and refine symbol timing recovery, carrier recovery, and equalization algorithmsPerform fixed-point modeling, quantization analysis, and algorithm optimization for hardware deploymentUse MATLAB and Simulink for modeling, simulation, and verification of DSP processing chainsCollaborate closely with FPGA design teams to translate algorithms into hardware-efficient architecturesSupport development of hardware architectures, including data-path specification and resource balancingParticipate in lab integration, system bring-up, and debugging of DSP and FPGA subsystemsAnalyze system performance and propose enhancements for robustness, efficiency, and scalability Minimum Qualifications Bachelor’s degree in Electrical Engineering or related fieldMinimum 5+ years of experience in the fieldStrong foundation in DSP theory and digital communication principlesExpertise in symbol timing recovery, equalization, carrier recovery, and related DSP componentsProficiency with MATLAB and Simulink for algorithm development and modelingExperience with fixed-point DSP, fixed-point arithmetic, and implementation constraints for hardwareFamiliarity with hardware architecture design principlesAbility to work effectively with FPGA and digital hardware engineersExperience with lab testing, hardware debugging, and system integrationExcellent problem-solving, communication, and technical-leadership skills Preferred Skills And Experience Master's in Electrical Engineering or related fieldPhD in Electrical Engineering or related field3+ years of experience with Verilog/VHDL or high-level synthesis toolsBackground in high-speed communication systems, FEC, or modem designKnowledge of DSP implementation on FPGAs or ASICsFamiliarity with HDL generation tools such as Simulink HDL Coder / HDL ToolboxExperience with free-space optical communication systemsExperience in a startup or fast paced agile development environment Additional Information Compensation bands are determined by role, level, location, and alignment with market data. Individual level and base pay is determined on a case-by-case basis and may vary based on job-related skills, education, experience, technical capabilities and internal equity. In addition to base salary, for full-time hires, you may also be eligible for long-term incentives, in the form of stock options, and access to medical, vision & dental coverage as well as access to a 401(k) retirement plan. Impulse Space’s spacecraft manufacturing business is subject to U.S. export regulations including the International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR). This position requires applicants to be either U.S. Persons (i.e., U.S. citizen, U.S. national, lawful permanent U.S. resident (green card holder), an individual granted asylum in the U.S., or an individual admitted in U.S. refugee status) or persons eligible to obtain an export license from the U.S. Departments of State, Commerce, or other applicable U.S. government agencies. Learn more about the ITAR here. Impulse Space is an Equal Opportunity Employer; employment with Impulse Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.