Senior Digital Hardware Designer

General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products, and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ professionals, we partner with industry leaders to expand the bounds of innovation in defense and scientific arenas.

About the role

GDMS has an immediate opening for a Senior Digital Design Engineer in Scottsdale, AZ. This position provides an opportunity to advance cutting-edge technology that supports national defense and intelligence services. Employees work closely with esteemed customers to develop solutions for high-stakes national security missions.

Senior Digital Design Engineers research, design, develop, and test electronic equipment and systems, including radar detection, communications equipment, circuitry components, computers, and Digital Signal Processing equipment.

Responsibilities

• Exercise creative thinking and ideation to advance business performance.
• Deliver innovative, flexible, integrated solutions to meet evolving customer needs.
• Support and engage in programs, projects, and practices aligned with GDMS culture and strategy.
• Comply with all policies and procedures.
• Follow industry trends to ensure GDMS services meet or exceed best practices.
• Provide technical leadership and direction to junior designers.
• Identify opportunities to apply AI for continuous improvement and innovation.
• Perform schematic capture.
• Design multi-layer Printed Circuit Boards with controlled impedance layers and blind micro-vias.
• Analyze and test for signal integrity, crosstalk, and other performance factors.
• Work with Micro Processors, Micro Controllers, FPGAs, and System-on-Chips.
• Demonstrate initiative and strong independent judgment.
• Technically lead and mentor less senior engineers.

Requirements

• Bachelor’s degree in Electrical Engineering or a related Science, Engineering, Technology, or Mathematics field.
• 8+ years of job-related experience, or a Master's degree plus 6 years of experience.
• U.S. citizenship is required due to the nature of work performed within our facilities.
• Department of Defense Secret security clearance is preferred at time of hire; applicants must meet eligibility requirements for access to classified information.

Skills

• Extensive experience designing multi-layer Printed Circuit Boards with controlled impedance layers and blind micro-vias.
• Familiarity with multiple families of Micro Processors, Micro Controllers, FPGAs, and System-on-Chips.
• Experience with schematic capture.
• Ability to analyze and test for signal integrity, crosstalk, and other performance factors.
• Preferred experience with Mentor design tools.
• Preferred experience with High Reliability or Space applications.
• Preferred experience with Worst Case Analysis and Stress Analysis.

Benefits

• Competitive benefits, including 401k matching and flex time off.
• Paid parental leave, healthcare benefits, and health & wellness programs.
• Employee resource and social groups.
• Flexible schedules with every other Friday off (9/80 schedule).
• Opportunities for continuous learning and development.
• Research-oriented work alongside award-winning teams.

Pay

Target salary range: USD $149,902.00/Yr. – USD $166,298.00/Yr. Actual pay may vary based on experience and geographic location.

Schedule

This position is fully on-site or hybrid/flexible as desired. On-site work will be based at the Scottsdale, AZ location.