Senior Digital Design Engineer

Job Responsibility

• Thoroughly understand various Standards and specifications regarding USB2, eUSB2, typeC, USBPD, TCPCI, BC1.2, I2C, SPI, SPMI; and map that knowledge to the needs of SoC product under design.
• Micro-architect the features and implementation details of the design IP.
• Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements. (Verilog/SystemVerilog).
• Conduct high-quality, area-optimal, low-power RTL design using industry-standard hardware description languages.
• Complete IP-level design verification activities, including testbench development, simulation, and debugging, to ensure functional correctness and coverage.
• Collaborate with architects, analog designers, test/product/quality/bench engineers and software team to define features, interfaces and integrate digital blocks.
• Participate in synthesis, static timing analysis (STA), and formal verification to meet timing, area, and power targets.
• Contribute to design for testability (DFT) implementation and verification.
• Generate comprehensive design documentation and participate in design reviews.
• Resolve design issues throughout the development lifecycle.
• Stay updated with the latest industry trends, tools, and methodologies in digital design.

Job Qualification

• Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, FPGA, Computer Architecture, Digital Verification.
• Minimum 3 years of experience in similar role of Digital Design & Architecture.
• Seeking 3-8 years total experience for this role.
• Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week full-day presence in NXP's Chandler office.
• Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.