Senior Design Verification (DV) Engineer

About the role

We are seeking a highly experienced Design Verification Engineer (DVE) to join our team. The DVE will be responsible for developing and verifying silicon IP, working closely with Architecture/Micro-architecture, Physical Design (PD), and Software teams.

Responsibilities

• Develop, optimize, and verify digital silicon IP using an existing C or Python model
• Create and maintain specifications, block diagrams, and detailed documentation/user guides
• Characterize the performance of digital silicon IP using industry standard tools and flows, including FPGA simulation and emulation

Qualifications

• At least 10 years of experience in Design Verification
• Experience leading a team of Design Verification Engineers
• Bachelor's/Master's degree in Electrical Engineering
• Experience with Synopsys tools and advanced node processes (below 12nm) is preferred
• Startup experience is preferred
• Government clearance is preferred

Pay

Compensation Range: $150,000–$220,000 per year (California)

Schedule

This is an on-site role requiring presence in the office 5 days a week. No hybrid option is available.