Senior Cell Modeling and Verification Engineer

About the role

The NVIDIA VLSI team is seeking a Senior Cell Modeling and Verification Engineer to contribute to the development of groundbreaking ASIC products. This role involves working closely with new NVIDIA hardware to ensure it meets design, feature, and quality objectives.

Responsibilities

• Develop behavioral models and perform verification for custom mixed signal design cells used across all NVIDIA products.
• Utilize Verilog, SystemVerilog, Perl, or Python to model, verify, emulate/prototype mixed-signal designs.
• Collaborate with cross-functional teams on library builds, cell integrations, ASIC verifications, and design-for-test (DFT) simulations.
• Document, implement, and deliver fully verified and high-performance RTL to meet design targets.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of relevant experience.
• Hands-on experience with RTL simulation and waveform debugging.
• Strong understanding of Verilog HDL.
• Scripting skills using Python or Perl.
• Fundamental knowledge of digital design and logic design concepts.

Qualifications

• Previous digital design experience is a plus.
• Experience running simulations in Verilog.
• Ability to collaborate with multiple teams and communicate technical details effectively.

Benefits

NVIDIA offers competitive compensation, including a base salary range of $136,000 - $218,500, along with equity and comprehensive benefits.

Pay

Base salary will be determined based on location, experience, and the pay of employees in similar positions.

Schedule

This posting is for an existing vacancy. Applications will be accepted until July 28, 2026.