Senior ASIC Verification Engineer

About the role

The NVIDIA Clocks Team is seeking a Senior ASIC Verification engineer to own validation of clocking and reset logic for Tegra and GPU products, develop test plans, automate flows, and collaborate with architecture and design teams to deliver high‑quality clock designs for data‑center, graphics, self‑driving and AI applications.

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop a scalable solution that works across platforms.
• Apply industry‑standard tools and state‑of‑the‑art verification methodologies, including coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
• Partner closely with clocks architecture and design teams to validate clock designs.
• Coordinate with internal and external teams across time zones.

Requirements

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry‑standard verification flows such as SV constraint random verification, UVM, Formal Verification, coverage metrics, profiling tools, Xprop, etc.
• Experience with block‑level and system‑level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/Python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience implementing test plans for pre‑silicon platforms.
• Understanding of DFT/IST is optional.

Skills

• System Verilog
• UVM
• C++
• Perl
• Python
• NVIDIA custom compilers and tools

Benefits

• Eligibility for equity awards
• Comprehensive benefits package

Pay

Base salary range: $136,000 – $218,500 USD for Level 3; $168,000 – $264,500 USD for Level 4.