Senior ASIC Timing Engineer

About the role

NVIDIA is seeking a motivated ASIC Timing Engineer to join our dynamic team. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where you can challenge yourself and contribute to cutting-edge projects that define the next era of computing. Your work will help drive innovation in GPUs, CPUs, LPUs, and SoCs, amplifying human inventiveness and intelligence.

Responsibilities

• Lead timing analysis and closure processes for NVIDIA’s GPUs, CPUs, LPUs, and SoCs at block, cluster, and full-chip levels.
• Collaborate with cross-functional teams (RTL, DFX, Clocks, and others) to devise timing closure strategies, create timing constraints, and drive timing and power convergence, including implementing ECOs.
• Play a pivotal role in the success of innovative projects and the advancement of NVIDIA’s technology by improving timing convergence flows in collaboration with methodology teams.
• Perform full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, including timing constraints generation and management.
• Analyze and fix timing paths through ECOs, including crosstalk and noise analysis.
• Optimize physical design (synthesis, placement, routing, logic restructuring) to improve timing and power.
• Apply expertise in deep sub-micron process nodes to model and converge timing.

Requirements

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 3+ years of experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, including timing constraints generation and management.
• Expertise in analyzing and fixing timing paths through ECOs, including crosstalk and noise analysis.
• Experience in physical design and optimization (e.g., synthesis, placement, routing, logic restructuring) to improve timing and power.
• In-depth knowledge of industry-standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.

Skills

• Background in domain-specific STA and timing convergence for GPUs, CPUs, LPUs, or SoCs (preferred).
• Experience with logic synthesis and equivalence checking/functional verification (FV).
• Understanding of DFT logic and experience with DFT timing closure for modes such as scan, BIST, etc.
• Experience with timing closure of digital logic/macros in AMS designs/IPs.
• Experience in methodology and/or flow development, as well as automation.

Pay

Base salary ranges are:

• Level 3: 136,000 USD – 218,500 USD
• Level 4: 168,000 USD – 264,500 USD

You will also be eligible for equity and benefits.

Applications for this role will be accepted until at least July 20, 2026.