Senior ASIC Physical Design Engineer, Netlisting

About the role

NVIDIA is seeking a Senior ASIC Physical Design Engineer, Netlisting to join their dynamic team. The ideal candidate should have a BS in Electrical or Computer Engineering with 5+ years' experience or an MS with 3+ years' experience. Key responsibilities include driving physical design of high-frequency and low-power CPUs, GPUs, SoCs at various levels, focusing on netlist-related aspects such as equivalence checking, asynchronous checking, logic synthesis, and netlist quality checks.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

Requirements

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience.
• Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools.
• Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.
• Experience in logic synthesis at either block or full-chip level, at project execution and/or flow development.
• Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise and in-depth knowledge of industry standard EDA tools in related fields.
• Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Qualifications

• Experience in logic synthesis and equivalence checking/FV.
• Familiarity with industry tools and flow.
• Strong hands-on debugging capability and problem-solving skills.
• Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.

Skills

• Experience with AI utilization to improve workflows and productivity.

Benefits

NVIDIA offers competitive compensation, including a base salary range of $136,000 - $218,500 for Level 3 and $168,000 - $264,500 for Level 4, along with equity and benefits. Applications are open until July 27, 2026.

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

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