Senior ASIC DFT Engineer, Silicon

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Work with multi-disciplined and multi-site teams of DFT engineers, RTL, Physical Designer Engineers, SOC DFT and Product Engineering.
• Learn and apply high-performance DFT techniques like SSN and HighBandwidth IJTAG, scaling DFT with minimal area overhead.
• Develop tests that can be used for Production in the automated test equipment (ATE) flow, and write basic to complex scripts to automate the DFT flow.
• Drive scan implementation and verification, ensuring coverage are met across all fault models.
• Manage Gate-Level Simulation (GLS) verification, tape-out (TO) signoff, pattern delivery, and post-silicon bring-up and debug.

Requirements

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience with Design for Test (DFT).
• Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc).
• Experience with one more than of the following: Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools and flow.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience working on DFT for complex subsystems with multiple physical partitions, understanding end-to-end SOC flows (Design, Verification, DFT, PD).
• Knowledge of high-performance DFT techniques like SSN and HighBandwidth IJTAG, scaling DFT with minimal area overhead.
• Proficiency with Spyglass-DFT, DFT Scan constraints, evaluating STA paths, and IJTAG (ICL, PDL extraction, and modeling with Siemens Tessent).
• Proficiency in coverage analysis, Gate-Level Simulation (GLS) debug, and silicon debug.
• Proficient with a scripting language such as Perl or Python.

Benefits

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Pay

$163000 - $237000 (USD)

Schedule

TBD