Senior ASIC Design Engineer - Agentic AI

About the role

NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to join the "AI for chip design" team. This role offers opportunities to innovate in chip design, impacting products ranging from consumer graphics to self-driving cars and artificial intelligence.

Responsibilities

• Document and deliver design guidelines for high performance, area and power efficient RTL implementation.
• Develop agentic AI solutions to craft micro-architecture, implement RTL, and deliver fully verified designs.
• Collaborate with other designers and tool owners to ensure design guidelines and agentic solutions meet requirements.
• Use AI technologies to solve complex chip design problems and drive innovation.
• Design and deploy LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems.
• Stay updated with the latest advancements in machine learning and AI to create impactful solutions.

Requirements

• Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
• 8+ years of meaningful work experience.
• Experience in micro-architecture and RTL development (Verilog) in complex designs.
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
• Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
• Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines, and vector databases.
• Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
• A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.

Qualifications

• Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
• 8+ years of meaningful work experience.
• Experience in micro-architecture and RTL development (Verilog) in complex designs.
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
• Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
• Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines, and vector databases.
• Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
• A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.

Skills

• Experience with digital systems and VLSI design.
• Knowledge of computer architecture and computer arithmetic.
• Proficiency in rapid prototyping using Python.
• Experience with large language models and multi-agent systems.
• Experience with RAG pipelines and vector databases.

Benefits

• Equity and benefits are available.

Pay

• Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5.

Schedule

• The posting is for an existing vacancy.