Semiconductor Device Modeling Engineer

About the role

The Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services that allow internal and external customers to bring winning products to the marketplace. Your work will directly enable design teams to get to market faster with leadership products based on innovative technologies. As a member of CDMG, you will be at the forefront of co-optimizing Intel's state-of-the-art process technology, enabling customers with diverse design needs to deliver best-in-class products for data-centric applications.

Responsibilities

• Characterize device behavior and generate/update device models for new technologies.
• Ensure robust and accurate model simulations.

Qualifications

Minimum qualifications

• Master's degree in Electrical Engineering or a related discipline with ≥3 years industry experience in semiconductor field; OR PhD in Electrical Engineering or related discipline with ≥1 year industry/research experience and dissertation focused on semiconductor devices or processes.
• Hands‑on experience in Python or C, Shell programming.
• Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.
• Ability to work independently after initial ramp‑up time.

Preferred qualifications

• Ph.D. in electrical engineering or related discipline with 3+ years industry experience in semiconductor field.
• Experience in BSIM models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators (HSPICE, SPECTRE, etc.).
• Understanding of corner, statistical and sub‑circuit models and their usages.
• Understanding of layout effects and models.
• Understanding of basic analog and digital circuit blocks and model interaction.
• Hands‑on experience in semiconductor device DC/CV characterization tools, techniques, and systems.
• Experience in test automation and RF/noise/reliability tests (a plus).
• Understanding of Aging Simulations and reliability methodologies and tools (a plus).
• Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.

Skills

• Python or C programming
• Shell scripting
• Semiconductor device physics
• Process flow, layout, circuit design and simulation
• BSIM and other compact models
• Extraction tools (ICCAP, MBP)
• Simulators (HSPICE, SPECTRE, etc.)
• Corner, statistical, sub‑circuit modeling
• Layout effects modeling
• Analog and digital circuit blocks
• DC/CV characterization
• Test automation, RF/noise/reliability testing
• Aging simulations, reliability methodologies
• Cadence design environment (schematic capture, analog design, virtuoso layout, DRC, LVS, layout extraction)

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $149,600.00 – $284,580.00 USD. Individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training.

Schedule

This role is eligible for Intel's hybrid work model, allowing employees to split time between on‑site at their assigned Intel site and off‑site.

Primary Location: US, California, Santa Clara. Additional Locations: US, Arizona, Phoenix; US, Oregon, Hillsboro.