Semiconductor Device Modeling Engineer

About the role

The Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP plays a crucial role in enabling Intel to deliver design, development, and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. As a member of CDMG, you will be involved in co-optimizing Intel's state-of-the-art process technology, supporting compact modeling activities for Intel's new technologies.

Responsibilities

• Support compact modeling activities for Intel's new technologies.
• Collaborate with cross-functional teams to develop and refine semiconductor device models.
• Develop and maintain compact models for advanced node technologies such as FinFET and GAA.
• Contribute to the understanding and implementation of layout-dependent effects and their impact on device and circuit performance.
• Develop methodologies for device targeting and benchmarking circuits, including statistical variation models.
• Use machine learning algorithms for data analysis and compact model development.

Requirements

• Bachelor's degree in Electrical Engineering or a related discipline with 5+ years of industry experience in the semiconductor field; or Master's degree in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline.
• Graduate coursework or research experience in semiconductor device physics.
• 1+ years' experience with Python scripting for data analysis, automation, and documentation.
• Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
• Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
• Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance.
• Development of methodologies for device targeting and benchmarking circuits, including corners and statistical variation models.
• Modeling using Open Model Interface (OMI).
• Strong understanding of process flow, layout, and basic circuit design/simulation.
• Proven capability to collaborate across multiple teams and geographies.

Qualifications

• Bachelor's degree in Electrical Engineering or a related discipline with 5+ years of industry experience in the semiconductor field; or Master's degree in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline.
• Graduate coursework or research experience in semiconductor device physics.
• 1+ years' experience with Python scripting for data analysis, automation, and documentation.
• Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field.
• Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
• Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
• Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance.
• Development of methodologies for device targeting and benchmarking circuits, including statistical variation models.
• Modeling using Open Model Interface (OMI).
• Strong understanding of process flow, layout, and basic circuit design/simulation.
• Proven capability to collaborate across multiple teams and geographies.
• Experience with machine learning algorithms and their application in data analysis and compact model development.

Skills

• Python scripting for data analysis, automation, and documentation.
• Extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
• BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
• Layout-dependent effects (LDE) for FinFET or GAAFET technologies.
• Statistical variation models for device and circuit performance.
• Open Model Interface (OMI) for modeling.
• Process flow, layout, and basic circuit design/simulation.
• Machine learning algorithms for data analysis and compact model development.

Benefits

Intel offers a comprehensive benefits package designed to support your well-being and financial security. This includes health, retirement, and vacation benefits, as well as opportunities for professional growth and personal enrichment. For more details, visit Intel Benefits | Intel Careers.

Pay

The annual salary range for this role is $149,600.00 - 284,580.00 USD. Individual pay within this range is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role requires an on-site presence. For more information on the work model and location details, please refer to the job posting details.