SECURITY IP VERIFICATION ENGINEER

About the role

You will be part of a team that defines and realizes the Hardware Security IP and Subsystem. The role involves developing test plans, testbenches, verification models, and test strategies in partnership with the design team to achieve functional sign-off, comprehensive coverage, and power and performance optimization.

Responsibilities

• Craft test plans for Security IP and Subsystem verification.
• Develop UVM, SystemVerilog/Verilog, and C testbenches and tests.
• Debug test failures and issues.
• Contribute to the development and enhancement of design and verification methodologies shared across Arm.
• Mentor team members to ensure successful project completion.
• Collaborate with Project Management on initiatives, plans, and schedules.