RTL Power Optimization Engineer – New College Grad 2026

About the role

NVIDIA is seeking a skilled engineer to join our team focused on optimizing power efficiency for NVIDIA's next generation GPUs and Networking products. The ideal candidate will leverage AI and advanced design techniques to improve the performance and energy efficiency of these systems.

Responsibilities

• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools to improve product power efficiency.
• Develop and share best practices for performing pre-silicon power analysis.
• Perform comparative power analysis to spot trends and anomalies that warrant more scrutiny.
• Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
• Select and run a wide variety of workloads for power analysis.
• Prototype a new architectural feature in Verilog and analyze power.

Requirements

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design and VLSI concepts (or equivalent experience).
• Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low-power design patterns at the RTL level.
• Knowledge of backend flows such as logic synthesis and place-and-route, and how RTL decisions impact post-layout power and timing.
• Familiarity with RTL implementation of low-power techniques (e.g., clock gating, operand isolation, power gating strategies, multi-VT usage) and their trade-offs.
• Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes.
• Coursework and/or hands-on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems.
• Previous experience debugging RTL or gate-level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root-cause structures or scenarios.
• Strong Python programming skills for building automation scripts, data pipelines, and AI/ML-driven analysis flows for RTL power optimization.
• Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML-based insights to both design and tools teams.

Qualifications

• Experience with industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent.
• Ability to prototype and analyze new architectural features in Verilog.
• Strong understanding of digital design principles and RTL implementation.
• Experience with machine learning and artificial intelligence techniques applied to EDA and silicon power problems.

Skills

• Advanced knowledge of digital design and VLSI concepts.
• Experience with AI and machine learning techniques.
• Proficiency in Python for automation and analysis.
• Excellent problem-solving and analytical skills.

Benefits

• Competitive base salary ranging from $116,000 to $189,750 for Level 2, and $136,000 to $218,500 for Level 3.
• Equity and comprehensive benefits package.

Pay

• Base salary range: $116,000 - $189,750 for Level 2, and $136,000 - $218,500 for Level 3.

Schedule

• Full-time position.

Contact Information

If you are interested in this opportunity, please apply at the provided link. Applications will be accepted until July 25, 2026.