RTL integration Engineer

About the role

The candidate will perform IP integration and IP test/debug mode verification at the SoC level. This role involves creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates. Additionally, the candidate will handle synthesis, palladium modeling, and STA support. Strong debugging skills are required.

Responsibilities

• Perform IP integration and verification at the SoC level
• Create RTL designs and perform linting
• Execute Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis for RTL and gate-level designs
• Handle synthesis, palladium modeling, and Static Timing Analysis (STA) support
• Debug zero-delay and SDF simulation failures
• Conduct gate-level simulation (GLS)

Requirements

• Extensive knowledge of implementation, synthesis, and timing issues
• Strong understanding of UVM and SystemVerilog
• Deep familiarity with zero-delay and SDF simulations, including debugging failures
• Proven experience in gate-level simulation (GLS)
• Familiarity with Clock Domain Crossing (CDC) analysis for RTL and gate-level designs
• Experience with simulation tools such as NCSim and VCS
• Ability to work independently with minimal supervision
• Experience working within a global team and dynamic environment
• Strong ability to quickly learn and adapt to new tools and methodologies
• Excellent communication skills

Qualifications

Bachelor’s degree and 12+ years of related experience.

Pay

The annual base salary range for this position is USD 143,800 to USD 230,000.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(K) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Paid holidays, sick leave, and vacation time
• Paid Family Leave and other leaves of absence, as applicable by law