RTL Design Engineer

About the role

We are seeking an experienced RTL Engineer to join our team. You will be responsible for designing and implementing design verification strategies for our AI chips, which are designed to handle both prefill and decode workloads efficiently.

Responsibilities

• Develop and implement design verification strategies for both our existing and upcoming ASIC designs.
• Work closely with the uArch team to ensure that blocks meet timing and area constraints.
• Implement a block to efficiently compute floating point math operators.
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints.

Requirements

• At least 5 years of work experience in RTL development.
• Experience with high-speed digital logic.
• Proficiency in standard RTL design and synthesis tools.
• Familiarity with verification work and writing test benches.
• Able to learn quickly about transformers and other aspects of modern artificial intelligence.
• Willing to start quickly.

Qualifications

• Strong candidates may also have experience with PCIe, Ethernet, or HBM technologies.
• Familiarity with modern ML and LLM model architectures.
• Familiarity with numerical representations and functions.
• Ability to program with Python or another scripting language.

Benefits

• Medical, dental, and vision packages with generous premium coverage.
• $500 per month credit for waiving medical benefits.
• Housing subsidy of $2k per month for those living within walking distance of the office.
• Relocation support for those moving to San Jose (Santana Row).
• Variety of wellness benefits covering fitness, mental health, and more.
• Daily lunch + dinner in our office.
• Unlimited compute budget subject to ROI justification.

Pay

Compensation range: $150K - $275K.

Schedule

Full-time position based in San Jose (Santana Row).