Research Computer Scientist, Reconfigurable Computer Architecture

About the role

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications, and artificial intelligence technologies. ISI's faculty, professional staff, and graduate students conduct extraordinary information sciences research at locations in Arlington, Virginia; Marina del Rey, California; and Waltham, Massachusetts.

ISI's Computational Systems and Technology Division is seeking a Research Computer Scientist to lead research and development in reconfigurable computer architectures. The position will focus on programmable compute and control structures that can rapidly switch among signal-processing, communications, and related workloads while meeting demanding throughput, latency, power, and resource constraints. The scientist will develop architectural concepts, models, and prototypes; guide implementation and evaluation across hardware and software; and work with interdisciplinary teams to mature architectures for sponsored research and transition. Initial applications may include adaptive communications and coding, a multifunction RF system on chip, or related efforts, depending on awards and program direction.

The Reconfigurable Computing Group turns ambitious computing ideas into working hardware. Its researchers connect architecture, algorithms, and implementation, taking designs from early concepts through FPGA demonstrations and custom silicon development. The group also develops tools that make these systems programmable and verifiable, including AI-assisted methods for hardware design, testing, device characterization, and debugging.

This position is based in ISI's Arlington, Virginia office.

Responsibilities

Architecture and research

• Define and evolve reconfigurable architectural components, including processing elements, configurable compute fabrics, control and scheduling mechanisms, on-chip communication, memory and data movement, and interfaces to external systems.
• Formulate research questions and conduct trade studies involving rapid reconfiguration, determinism, throughput, energy efficiency, scalability, and programmability.
• Develop performance models and publishable technical results.

Prototype and evaluation

• Lead architecture modeling, RTL and FPGA prototyping, integration, verification, and benchmarking in collaboration with hardware, compiler, software, and application researchers.
• Investigate AI-assisted and agent-based methods for HDL design, testbench generation, and design exploration, and verify generated artifacts against functional and performance requirements.
• Establish representative workloads and measurable requirements, analyze bottlenecks, and guide design changes.
• Support application demonstrations such as adaptive encoding and decoding workflows or multifunction RF signal processing, as program needs warrant.

Technical leadership and sponsored research

• Provide technical direction to researchers, engineers, and students; coordinate architecture deliverables across collaborating organizations; document designs and results for sponsors; contribute to proposals, reports, publications, and presentations; and engage prospective transition partners regarding architecture requirements and evaluation.

Qualifications

Minimum qualifications

• Doctorate in computer engineering, electrical engineering, computer science, or a closely related field.
• Demonstrated research contributions in computer architecture or reconfigurable computing.