Quantum Qubit Design Engineer
. Use - for lists. Use
for prose. No job title heading. No Job ID. Remove boilerplate: cookie/navigation/legal/EEO/equal-opportunity/scam-warning, duplicated lines, application instructions. Keep substantive info.
We need sections: About the role (maybe from first paragraph), Responsibilities (Key Responsibilities), Qualifications (Minimum Qualifications, Preferred Qualifications), Benefits (if present), Pay (Annual Salary Range), Schedule (Work Model). Also maybe "Location" but not required heading; we can include in a paragraph.
We must not create sections with filler like "commensurate with experience". We have actual content for Benefits, Pay, Schedule.
We need to preserve all substantive info, not invent or summarize away detail. So we need to include all details from the posting, but we can format as lists where appropriate.
We must not repeat job title. No Job ID.
We need to remove duplicated lines: there are duplicate "Benefits" sections etc. We'll combine.
Let's extract content.
Job Description paragraph: "Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey"
We should not include "Apply now" maybe considered application instruction? The instruction says remove application instructions. "Apply now and be part of this extraordinary journey" is an application instruction. So we should remove that sentence. Also "Ready to help build the future of quantum computing?" maybe also call to action. We'll remove that as well.
Thus keep the descriptive prose up to that point.
Key Responsibilities list: many bullet-like sentences. We'll convert each line into
- .
List items:
- Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules
- Architect qubit and readout element standard cell design and automation
- Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability
- Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology
- Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors
- Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts
- Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors
- Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs
- Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk
- Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors
- Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI
- Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff
- Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Qubit processor to ASIC control
- Designing and taping out electrical characterization test structures to characterize qubit and interconnect performance and yield
- Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable thermal analysis of large scale quantum processors
- Implement PDK collateral into customized design environments and create and maintain customized design workflows for qubit processors
- Working with external customers to understand their needs and provide solutions based on Intel's quantum PDK
- Ensure successful implementation of Intel quantum PDK design collateral and EDA tool capabilities for External Customers
- Ensuring external customer designs are successfully taped out with silicon run to end-of-line on schedule
Also there is a paragraph after responsibilities: "As a successful candidate, you must possess ..." That's actually qualifications/skills list. We'll treat that as part of Qualifications/Skills.
But there is also a separate "Qualifications" section later with Minimum and Preferred.
We need to avoid duplication. The "As a successful candidate..." list includes skills: Excellent communication..., Keen experimental insight..., High motivation..., Creativity..., Strong analytical..., Collaborative mindset..., Adaptability..., Leadership potential..., Passion...
We should include those under Skills or Requirements. Since we have a Qualifications section, we could put those under Skills or Requirements. The instruction says use headings like Skills, Requirements, Qualifications. We can have a Skills section for those soft skills.
Thus we will have sections:
- About the role (maybe heading About the role) with the descriptive paragraph (excluding apply now).
- Responsibilities (h3) with ul list.
- Skills (h3) with ul list of those soft skills.
- Qualifications (h3) with two sub-sections? Could just have ul for Minimum Qualifications and another ul for Preferred Qualifications. Or we could have headings inside? But only allowed headings are h3 for section headings. We could have two separate sections: Minimum Qualifications and Preferred Qualifications each as h3? The instruction says use h3 for section headings (e.g. About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule). It doesn't forbid other headings like Minimum Qualifications, but they said e.g. list. Safer to keep Qualifications as one section and inside we can have paragraphs or lists. We'll put Minimum Qualifications as a
or
. We'll include both.
- Benefits (h3) with ul list of benefits described: "At Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion." Also later: "We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel." We'll combine.
We should not include links like "Go to Intel Benefits | Intel Careers". That's maybe application instruction? It's a reference. Might be okay to keep as prose. But we should avoid navigation? It's not navigation. We'll keep.
- Pay (h3) with p containing the Annual Salary Range: "$141,910.00 - 269,100.00 USD". Also note that individual pay determined by location etc. We'll include that.
- Schedule (h3) with p containing Work Model: "This role will require an on-site presence." Also note shift: "Job Type Experienced Hire Shift Shift 1 (United States of America)". Also we could include location info. But schedule heading is for schedule/shift. We'll include shift and work model.
We also have location info: Primary Location etc. Could be included in a paragraph under maybe About the role or separate? Not required heading. We'll add a paragraph under About the role maybe after description.
We must not include duplicated lines: there were duplicate Benefits sections etc. We'll combine.
We must not include boilerplate like EEO, etc. Remove that.
We must not include "Posting Statement", "Position of Trust N/A", "ADDITIONAL INFORMATION", etc.
Now produce HTML fragment.
Structure:
About the role
Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing.
Primary Location: US, Oregon, Hillsboro. Additional Locations: US, Arizona, Phoenix; US, California, Folsom; US, California, Santa Clara; US, Massachusetts, Beaver Brook; US, New York, New York; US, Pennsylvania, Allentown; US, Texas, Austin.
Responsibilities
- Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules
- Architect qubit and readout element standard cell design and automation
- Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability
- Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology
- Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors
- Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts
- Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors
- Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs
- Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk
- Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors
- Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI
- Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff
- Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Q
for prose. No job title heading. No Job ID. Remove boilerplate: cookie/navigation/legal/EEO/equal-opportunity/scam-warning, duplicated lines, application instructions. Keep substantive info. We need sections: About the role (maybe from first paragraph), Responsibilities (Key Responsibilities), Qualifications (Minimum Qualifications, Preferred Qualifications), Benefits (if present), Pay (Annual Salary Range), Schedule (Work Model). Also maybe "Location" but not required heading; we can include in a paragraph. We must not create sections with filler like "commensurate with experience". We have actual content for Benefits, Pay, Schedule. We need to preserve all substantive info, not invent or summarize away detail. So we need to include all details from the posting, but we can format as lists where appropriate. We must not repeat job title. No Job ID. We need to remove duplicated lines: there are duplicate "Benefits" sections etc. We'll combine. Let's extract content. Job Description paragraph: "Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey" We should not include "Apply now" maybe considered application instruction? The instruction says remove application instructions. "Apply now and be part of this extraordinary journey" is an application instruction. So we should remove that sentence. Also "Ready to help build the future of quantum computing?" maybe also call to action. We'll remove that as well. Thus keep the descriptive prose up to that point. Key Responsibilities list: many bullet-like sentences. We'll convert each line into
or
- . We'll include both.
- Benefits (h3) with ul list of benefits described: "At Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion." Also later: "We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel." We'll combine.
We should not include links like "Go to Intel Benefits | Intel Careers". That's maybe application instruction? It's a reference. Might be okay to keep as prose. But we should avoid navigation? It's not navigation. We'll keep.
- Pay (h3) with p containing the Annual Salary Range: "$141,910.00 - 269,100.00 USD". Also note that individual pay determined by location etc. We'll include that.
- Schedule (h3) with p containing Work Model: "This role will require an on-site presence." Also note shift: "Job Type Experienced Hire Shift Shift 1 (United States of America)". Also we could include location info. But schedule heading is for schedule/shift. We'll include shift and work model.
We also have location info: Primary Location etc. Could be included in a paragraph under maybe About the role or separate? Not required heading. We'll add a paragraph under About the role maybe after description.
We must not include duplicated lines: there were duplicate Benefits sections etc. We'll combine.
We must not include boilerplate like EEO, etc. Remove that.
We must not include "Posting Statement", "Position of Trust N/A", "ADDITIONAL INFORMATION", etc.
Now produce HTML fragment.
Structure:
- Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules
- Architect qubit and readout element standard cell design and automation
- Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability
- Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology
- Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors
- Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts
- Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors
- Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs
- Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk
- Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors
- Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI
- Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff
- Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Q
About the role
Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing.
Primary Location: US, Oregon, Hillsboro. Additional Locations: US, Arizona, Phoenix; US, California, Folsom; US, California, Santa Clara; US, Massachusetts, Beaver Brook; US, New York, New York; US, Pennsylvania, Allentown; US, Texas, Austin.